View DA7212_8755344.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 1 of 129 ? 2015 dialog semiconductor g eneral d escription the DA7212 is an ultra - low power audio codec targeting portable audio devices. the input paths support stereo fm line input and up to four analogue (or two analogue and two digital) microphones with two independent microphone biases. comprehensive analogue mixing and bypa ss paths to the output drivers are available. the headphone output is true - ground class g with integrated charge pump. there is also a differential class ab speaker driver that can serve as a mono lineout. digital audio transfer to/from the external proces sor is via a bi - directional digital audio interface that supports all common sample rates and formats. the device may be operated in slave or master modes using the internal pll which may be bypassed if not required. to fully optimise each customer applica tion, a range of built in filtering, equalisation and audio enhancements are available. these are accessible by the processor over the i2c serial interface. key features 100 db snr st ereo audio playback into 16 ? headphones 3.1 mw power consumption for ste reo dac to headphone playback 1.2 w mono speaker driver 650 w mono voice record stereo digital microphone support supports up to four analogue microphones two low - noise microphone - bias outputs low - power pll provides system clocking and audio sample rate flexibility built - in 5 - band equaliser, alc and noise - gate functions built - in beep generator integrated system controller to eliminate pops and clicks minimised external component count 34 - ball wl - csp (4.54 mm x 1.66 mm) package staggered 0.5 mm pitch for easy pcb routing allowing low cost manufacture applications personal media players audio headphone/headsets wearables embedded applications arduino compatible development systems figure 1 : the DA7212 chip
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 2 of 129 ? 2015 dialog semiconductor contents general description ................................ ................................ ................................ ............................. 1 key features ................................ ................................ ................................ ................................ ......... 1 applications ................................ ................................ ................................ ................................ ......... 1 contents ................................ ................................ ................................ ................................ ............... 2 figures ................................ ................................ ................................ ................................ .................. 4 tables ................................ ................................ ................................ ................................ ................... 5 1 terms and definitions ................................ ................................ ................................ ................... 7 2 block diagr am ................................ ................................ ................................ ................................ 8 3 pinout ................................ ................................ ................................ ................................ ............. 9 4 absolute maximum ratings ................................ ................................ ................................ ........ 11 5 recommended operating conditions ................................ ................................ ........................ 11 6 electrical characteristics ................................ ................................ ................................ ............ 12 7 parametric specifications ................................ ................................ ................................ ........... 13 8 digital signal processing ................................ ................................ ................................ ............ 16 9 audio outputs ................................ ................................ ................................ .............................. 18 10 clock generation ................................ ................................ ................................ ......................... 22 11 phase locked loop (pll) ................................ ................................ ................................ ............. 22 12 digital interfaces ................................ ................................ ................................ ......................... 23 12.1 codec start - up time ................................ ................................ ................................ ............. 26 13 functional description ................................ ................................ ................................ ................ 27 13.1 general description ................................ ................................ ................................ ............. 27 13.2 input signal chain ................................ ................................ ................................ ................ 28 13.3 microphone inputs ................................ ................................ ................................ ............... 29 13.4 digital microphones ................................ ................................ ................................ ............. 29 13.5 auxiliary inputs ................................ ................................ ................................ .................... 30 13.6 input mixers ................................ ................................ ................................ ......................... 31 13.7 stereo audio adc ................................ ................................ ................................ ............... 31 13.8 automatic level control (alc) ................................ ................................ ............................. 32 13.9 beep generator and controller ................................ ................................ ............................ 34 13.10 output signal chain ................................ ................................ ................................ ............. 35 13.11 stereo audio dac ................................ ................................ ................................ ............... 35 13.12 output mixer ................................ ................................ ................................ ........................ 36 13.13 headphone amplifier ................................ ................................ ................................ ........... 36 13.14 speaker amplifier ................................ ................................ ................................ ................ 37 13.15 charge pump control ................................ ................................ ................................ ........... 37 13.16 charge pump clock co ntrol ................................ ................................ ................................ . 39 13.17 boosting the charge pump using demand feedback control ................................ ............... 39 13.17.1 tracking the demands on the charge pump output ................................ ............. 39 13.17.1.1 cp_mchange = 00 (manual mode) ................................ .............. 39 13.17.1.2 cp_mchange = 01 (tracking the pga gain setting) ..................... 39 13.17.1.3 cp_mchange = 10 (tracking the dac signal setting) .................. 39 13.17.1.4 cp_mchange = 11 (tracking the output signal magnitude) .......... 39
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 3 of 129 ? 2015 dialog semiconductor 13.17.2 specifying clock frequencies when tracking the charge pump output demand ... 40 13.17.3 controlling the boost of the charge pump clock - frequency ................................ . 40 13.17.3.1 cp_analogue_lvl = 01 ................................ ............................. 40 13.17.3.2 cp_analogue_lvl = 10 ................................ ............................. 40 13.18 other charge pump controls ................................ ................................ ............................... 41 13.19 digital signal processing engine ................................ ................................ ......................... 42 13.20 variab le high - pass audio filter (dc cut) ................................ ................................ ............. 42 13.21 variable high pass filter (wind noise filtering) ................................ ................................ ..... 43 13.22 dac 5 - band equaliser ................................ ................................ ................................ ......... 44 13.23 soft mute ................................ ................................ ................................ ............................. 46 13.24 playback noise - gate ................................ ................................ ................................ ............ 46 13.25 clock modes ................................ ................................ ................................ ....................... 47 13.26 pll bypass mode ................................ ................................ ................................ ............... 48 13.26.1 normal pll mode (dai master) ................................ ................................ .......... 49 13.26.2 example calculation of the feedback divider setting: ................................ ........... 50 13.27 srm pll mode (dai slave) ................................ ................................ ................................ 51 13.28 32 khz pll mode (dai master) ................................ ................................ .......................... 51 13.29 operating with a 2 mhz to 5 mhz mclk ................................ ................................ ............ 51 13.30 mi xed sample rates ................................ ................................ ................................ ............. 51 13.31 i2c control interface ................................ ................................ ................................ ............ 52 13.32 details of the i2c control interface protocol ................................ ................................ ........ 53 13.33 digital audio interface (dai) ................................ ................................ ................................ 55 13.34 i2s mode ................................ ................................ ................................ ............................. 56 13.35 left justified mode ................................ ................................ ................................ ............... 56 13.36 right justified mode ................................ ................................ ................................ ............. 56 13.37 dsp mode ................................ ................................ ................................ ........................... 57 13.38 time division multiplexing (tdm) mode ................................ ................................ .............. 58 13.38.1 configuration of the digital audio interface ................................ .......................... 59 13.39 pop - free and click - free start - up using the sys tem controllers ................................ ............. 59 13.39.1 level 1 system controller (scl1) ................................ ................................ ........ 59 13.39.2 level 2 system controller (scl2) ................................ ................................ ........ 60 13.40 powe r supply C standby mode ................................ ................................ ............................ 60 13.40.1 entering standby mode ................................ ................................ ........................ 60 13.40.2 exiting standby mode ................................ ................................ .......................... 60 14 register definitions ................................ ................................ ................................ ..................... 61 14.1 register map ................................ ................................ ................................ ....................... 61 14.2 status registers ................................ ................................ ................................ ................... 67 14.3 system initialisation registers ................................ ................................ .............................. 72 14.4 input gain/select filter registers ................................ ................................ ........................... 78 14.5 output gain - filter registers ................................ ................................ ................................ ... 83 14.6 system controller registers ................................ ................................ ................................ .. 91 14.7 control registers ................................ ................................ ................................ .................. 93 14.8 mixed sample mode registers ................................ ................................ ........................... 102 14.9 configuration registers ................................ ................................ ................................ ...... 103 15 package information ................................ ................................ ................................ ................. 118 15.1 package outlines ................................ ................................ ................................ ............... 118 15.2 soldering information ................................ ................................ ................................ ........ 119
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 4 of 129 ? 2015 dialog semiconductor 16 ordering information ................................ ................................ ................................ ................ 119 applications information ................................ ................................ ........................... 120 appendix a a.1 codec initialisation ................................ ................................ ................................ ............ 120 a.2 automatic alc calibration ................................ ................................ ................................ . 120 a.3 troubleshooting ................................ ................................ ................................ ................ 121 components ................................ ................................ ................................ ................ 122 appendix b b.1 audio inputs ................................ ................................ ................................ ...................... 122 b.2 microphone bias ................................ ................................ ................................ ................ 123 b.3 digital microphone ................................ ................................ ................................ ............ 123 b.4 audio outputs ................................ ................................ ................................ .................... 123 b.5 headphone charge pump ................................ ................................ ................................ . 124 b.6 digital interfaces ................................ ................................ ................................ ................ 125 b.7 references ................................ ................................ ................................ ........................ 126 b.8 supplies ................................ ................................ ................................ ............................ 126 b.9 ground ................................ ................................ ................................ .............................. 127 b.10 capacitor selection ................................ ................................ ................................ ............ 127 pcb layout guidelines ................................ ................................ ............................... 128 appendix c c.1 layout and schematic support ................................ ................................ .......................... 128 c.2 general recommendations ................................ ................................ ................................ 128 figures figure 1: the DA7212 chip ................................ ................................ ................................ .................... 1 figure 2: block diagram showing component values for a typical application ................................ ...... 8 figure 3: DA7212 ball layout ................................ ................................ ................................ ................. 9 figure 4: i2c bus timing ................................ ................................ ................................ ...................... 24 figure 5: digital audio interface timing diagram ................................ ................................ .................. 25 figure 6: audio input routing and gain ranges ................................ ................................ .................... 28 figure 7: typical microphone application for mic1 (mic2 is similar) ................................ .................. 29 figure 8: digital microphone timing example ................................ ................................ ...................... 30 figure 9: principle of operation of the alc ................................ ................................ ......................... 32 figure 10: attack, delay and hold parameters ................................ ................................ ..................... 33 figure 11 : analogue output signal paths and gain ranges ................................ ................................ .. 35 figure 12: input (clk) and output clocks (cp_clk and cp_clk2) at cp_fcontrol = 010 .................. 39 figure 13: adc and dac dc blocking (cut - off frequency setting 00 to 11, 16 khz) ...................... 42 figure 14: wind noise high - pass filter (cut - off frequency setting 000 to 111, 16 khz) .................... 43 figure 15: equaliser filter band 1 frequency response at fs = 48 khz ................................ ............... 44 figure 16: equaliser filter band 2 frequency response at fs = 48 khz ................................ ............... 45 figure 17: equaliser filter band 3 frequency respon se at fs = 48 khz ................................ ............... 45 figure 18: equaliser filter band 4 frequency response at fs = 48 khz ................................ ............... 45 figure 19: equaliser filter band 5 frequency response at fs = 48 khz ................................ ............... 46 figure 20: schematic of the i2c control interface bus ................................ ................................ ........ 52 figure 21 timing of i2c start and stop conditions ................................ ................................ ....... 53 figure 22: i2c byte write (sda signal) ................................ ................................ ................................ 53 figure 23: examples of the i2c byte read (sda line) ................................ ................................ ......... 53 f igure 24: examples of i2c page read (sda line) ................................ ................................ .............. 54 figure 25: i2c page write (sda line) ................................ ................................ ................................ ... 54 figure 26: i2c repeated write (sda line) ................................ ................................ ............................ 54 figure 27: master mode (dai_clk_en = 1) ................................ ................................ ....................... 55 figure 28: sl ave mode (dai_clk_en = 0) ................................ ................................ ......................... 55 figure 29: i2s mode ................................ ................................ ................................ ............................ 56 figure 30: left justified mode ................................ ................................ ................................ .............. 56
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 5 of 129 ? 2015 dialog semiconductor figure 31: right justified mode ................................ ................................ ................................ ............ 56 figure 32: dsp mode ................................ ................................ ................................ .......................... 57 figure 33: tdm example (slave mode) ................................ ................................ ............................... 58 figure 34: tdm mode (left justified mode) ................................ ................................ .......................... 58 figure 35: DA7212 package outline drawing ................................ ................................ .................... 118 figure 36: micbias decoupling ................................ ................................ ................................ ........ 123 figure 37: recommended headphone layout ................................ ................................ ................... 123 figure 38: charge pump decoupling ................................ ................................ ................................ . 124 figure 39: charge pump flying capacitor ................................ ................................ .......................... 124 figure 40: i2c pull ups ................................ ................................ ................................ ...................... 125 figure 41: reference capacitors ................................ ................................ ................................ ....... 126 figure 42: power supp ly decoupling ................................ ................................ ................................ . 126 figure 43: example layout ................................ ................................ ................................ ................. 128 tables table 1: pin descriptions ................................ ................................ ................................ ....................... 9 table 2: pin type definition ................................ ................................ ................................ .................. 10 table 3: absolute maximum ratings ................................ ................................ ................................ .... 11 table 4: recommended operating conditions ................................ ................................ ..................... 11 table 5: power consumption ................................ ................................ ................................ ............... 12 table 6: reference voltage generation ................................ ................................ ............................... 12 table 7: analog ue to digital converter (adc) ................................ ................................ ...................... 13 table 8: microphone bias ................................ ................................ ................................ .................... 14 table 9: input mixing units ................................ ................................ ................................ ................... 15 table 10: adc/dac digital high - pass filter cut - off frequencies in music mode ................................ .. 16 table 11: adc/dac digital high - pass filter cut - off frequencies in voice mode ................................ ... 16 table 12: dac 5 - band equali ser frequencies ................................ ................................ ..................... 17 table 13: beep generator ................................ ................................ ................................ .................... 17 table 14: digital to analogue converter (dac) ................................ ................................ ................... 18 table 1 5: class ab lineout amplifier / speaker ................................ ................................ .................... 19 table 16: true ground charge pump ................................ ................................ ................................ ... 20 table 17: true ground headphone amplifier ................................ ................................ ....................... 21 table 18: mclk input ................................ ................................ ................................ .......................... 22 table 19: pll mode ................................ ................................ ................................ ............................ 22 table 20: bypass mode ................................ ................................ ................................ ....................... 22 table 21: i/o characteristics ................................ ................................ ................................ ................ 23 table 22: i2c control bus (vdd_io = 1.8 v) ................................ ................................ ....................... 24 table 23: digital audio interface timing (i2s/dsp in master/slave mode) ................................ .......... 25 table 24: codec start - up times ................................ ................................ ................................ ........... 26 table 25: dtmf keypad frequencies ................................ ................................ ................................ .. 34 table 26: charge pump output voltage control ................................ ................................ ................... 37 table 27: cp_thresh_vdd2 settings in dac_vol mode (cp_mchange = 10) ......................... 38 table 28: cp_thresh_vdd2 settings in signal size mode (cp_mchange = 11) ......................... 38 table 29: charge pump current load cont rol ................................ ................................ ....................... 41 table 30: adc/dac digital high - pass filter specifications in audio mode ................................ ........... 42 table 31: wind noise high - pass filter specifications ................................ ................................ ........... 43 table 32: dac 5 - band equaliser turnover/centre frequencies ................................ ............................ 44 table 33: pll clock modes ................................ ................................ ................................ ................. 47 table 34: sample rate control register and corresponding system clock frequency ........................... 48 table 35: pll input divider ................................ ................................ ................................ .................. 49 table 36: example pll configurations ................................ ................................ ................................ 50 table 37: orderin g information ................................ ................................ ................................ .......... 119 table 38: offset calibration, mic1_p and mic2_p single ended, slave mode ................................ . 121 table 39: audio inputs ................................ ................................ ................................ ....................... 122 table 40: microphone bias ................................ ................................ ................................ ................ 123 table 41: digital microphon es ................................ ................................ ................................ ........... 123 table 42: headphone outputs ................................ ................................ ................................ ........... 123
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 6 of 129 ? 2015 dialog semiconductor table 43: speaker outputs ................................ ................................ ................................ ................ 124 table 44: headphone charge pump ................................ ................................ ................................ .. 124 table 45: digital interfaces - i2c ................................ ................................ ................................ ....... 125 table 46: digital interfaces - i2s ................................ ................................ ................................ ....... 125 table 47: references ................................ ................................ ................................ ........................ 126 table 48: power supplies ................................ ................................ ................................ .................. 126 table 49: ground ................................ ................................ ................................ ............................... 127 table 50: recommended capacitor types ................................ ................................ ......................... 127
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 7 of 129 ? 2015 dialog semiconductor 1 terms and d efinitions adc analogue digital converter alc automatic level control dac digital audio converter dai digital audio interface dtmf dual tone multi frequency i2c inter - integrated circuit interface i2s inter - ic sound pll phase locked loop psr r power supply rejection ratio snr signal to noise ratio tdm time division multiplexing thd+n total harmonic distortion plus noise wl - csp wafer level - chip scale packaging
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 8 of 129 ? 2015 dialog semiconductor 2 block d iagram figure 2 : block diagram showing component values for a typical application adc digital filter : analogue filter block inco rporating wind noise filtering and automatic level control (alc). dac digital filter : digital filter block incorporating digital mixing, digital volume control, a 5 band equaliser and a noise gate . beep generator : the beep generator block has two sine wav e generators, each of which can be independently controlled. output frequency is controllable in 10 hz step sizes, and output gain is controllable in 3 db steps from 0 db to 45 db. the beep generator block can also output standard dtmf keypad frequencies ( see table 25 ). m i c 1 _ p / d m i c c l k a d c _ l a d c d i g i t a l f i l t e r s w i n d n o i s e f i l t e r i n g , a u t o m a t i c l e v e l c o n t r o l ( a l c ) d a c d i g i t a l f i l t e r s d i g i t a l m i x e r , d i g i t a l v o l u m e , 5 b a n d e q u a l i s e r , n o i s e g a t e d a c _ l a u x _ l a u x _ r a u x i n p u t s p _ p p l l + m i x i n _ l m i c 2 _ p + m i x i n _ r a d c _ r d a c _ r + + g n d _ c p b c l k d a t o u t w c l k d a t i n d i g i t a l a u d i o i n t e r f a c e ( d a i ) s p _ n l i n e _ a m p c h a r g e p u m p h p c s p h p c s n 1 u f 1 u f v d i g v m i d g n d _ a h e a d p h o n e s h p _ l _ a m p h p _ r _ a m p h p _ l h p _ r c o n t r o l i n t e r f a c e s d a s c l 1 f h p c f n h p c f p 1 u f d a c r e f b i a s m i c _ 1 _ a m p m i c _ 2 _ a m p m i c 1 _ n / d m i c i n m i c b i a s 1 m i c b i a s 2 m i c 2 _ n m c l k g n d _ s e n s e v d d _ s p v r e f m i c b i a s 1 m i c b i a s 2 1 f a u x _ l _ a m p a u x _ r _ a m p d a 7 2 1 2 v d d _ m i c b e e p g e n e r a t o r + v d d _ i o v d d _ a l d o
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 9 of 129 ? 2015 dialog semiconductor 3 pinout figure 3 : DA7212 ball layout table 1 : pin descriptions pin name bump/pin function alternate function c lass audio inputs mic1_p c17 differential mic. input 1 (pos) / single - ended mic. input 1 (left) digital mic. clock (dmicclk) ai/do mic1_n b16 differential mic. input 1 (neg) / single - ended mic. input 2 (left) digital mic. data (dmicin) ai/di mic2_p d16 differential mic. input 2 (pos) / single - ended mic. input 1 (right) ai mic2_n c15 differential mic. input 2 (neg) / single - ended mic. input 2 (right) ai aux_l c13 single - ended auxiliary input left ai aux_r d14 single - ended auxiliary input right ai micbias1 a15 microphone bias output 1 ao micbias2 a17 microphone bias output 2 ao audio ouputs hp_l a3 true - ground headphone output left ao hp_r a5 true - ground headphone output right ao sp_p b12 differential speaker output (pos) ao sp_n a13 differential speaker output (neg) ao audio charge pump hpcsp a1 charge pump reservoir capacitor (pos) aio hpcsn c1 charge pump reservoir capacitor (neg) aio hpcfp d2 charge pump flyback capacitor (pos) aio h p c f p b c l k h p c f n d a t i n w c l k s c l d a t o u t s d a v d d _ i o v d i g a u x _ l a u x _ r m i c 2 _ n h p c s n g n d _ c p g n d _ s e n s e h p _ l h p _ r v d d _ a v r e f d a c r e f v m i d g n d _ a s p _ p v d d _ s p s p _ n v d d _ m i c m i c b i a s 1 m i c 1 _ n m i c 2 _ p h p c s p m i c b i a s 2 m i c 1 _ p 1 2 3 4 5 6 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 a b c d 7 1 2 3 4 5 6 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 7 s e n s i t i v e a n a l o g u e n o i s y d i g i t a l l o w p o w e r ( u p t o 1 0 0 m a ) m e d i u m p o w e r ( u p t o 5 0 0 m a ) q u i e t g r o u n d n o i s y g r o u n d v i e w f r o m a b o v e l i v e b u g k e y m c l k
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 10 of 129 ? 2015 dialog semiconductor pin name bump/pin function alternate function c lass hpcfn c3 charge pump flyback capacitor (neg) aio digital interfaces sda c9 i2c bi - directional data dio scl d8 i2c clock input di datin c5 dai data input dio datout c7 dai data output dio bclk d4 dai bit clock dio wclk d6 dai word clock (l/r select) dio mclk c11 master clock di references dacref a7 audio dac reference capacitor aio vmid a9 audio mid - rail reference capacitor aio gnd_sense b4 ground reference for headphone output ai vref b8 bandgap reference capacitor aio supplies vdd_a b6 supply for analogue circuits ps vdd_io d10 supply for digital interfaces ps vdd_sp a11 supply for speaker driver ps vdd_mic b14 supply for microphone bias circuits ps vdig d12 supply for digital circuits (ldo output) ps grounds gnd_a b10 analogue ground pg gnd_cp b2 digital ground/charge pump pg table 2 : pin type definition pin type description pin type description di digital input ai analog input do digital output ao analog output dio digital input/output aio analog input/output ps power supply pg power ground
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 11 of 129 ? 2015 dialog semiconductor 4 absolute maximum ratings table 3 : absolute maximum ratings parameter description conditions ( note 1 ) min max unit storage temperature - 65 +165 c t a operating temperature - 40 +85 c vdd_sp supply voltages - 0.3 6.0 v vdd_a - 0.3 2.75 v vdd_io vdd_mic - 0.3 5.5 v sda scl bclk wclk datin datout digital interface signals - 0.3 vdd_io + 0.3 v package thermal resistance 60 c/w esd susceptibility human body model 2 kv note 1 stre sses beyond those listed under a bsolute m aximum ratings may cause permanent damage to the device. these are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. 5 recommended operating conditions table 4 : recommended operating conditions parameter description conditions min typ max unit t a operating temperature - 40 +85 c vdd_a supply voltages 1.6 2.65 v vdd_io 1.5 3.6 v vdd_mic 1.8 3.6 v vdd_sp 0.95 5.25 v note 2 if the speaker output is not used then vdd_sp can be left unconnected
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 12 of 129 ? 2015 dialog semiconductor 6 electrical characteristics table 5 : power consumption description conditions ( note 3 ) min unit powerdown mode 5 a digital playback to lineout dac_l/r to line, 10 k? load 2.2 mw digital playback to headphone, no load dac_l/r to hp_l/r, quiescent 3.1 mw digital playback to headphone, with load dac_l/r to hp_l/r, 16 ? load, 0.1 mw at 0 dbfs 6.9 mw analogue bypass to lineout aux_l/r to line, 10 k? load 2.0 mw analogue bypass to headphone, no load aux_l/r to hp_l/r, quiescent 2.6 mw analogue bypass to headphone, with load aux_l/r to hp_l/r, 16 ? load, 0.1 mw at 0 dbfs 6.7 mw microphone stereo record mic_1/2 to adc_l/r 2.1 mw microphone stereo record and digital playback to headphone, no load mic_1/2 to adc_l/r and dac_l/r to hp_l/r, quiescent 4.8 mw microphone stereo record and digital playback to headphone, with load mic_1/2 to adc_l/r and dac_l/r to hp_l/r, 16 ? load, 0.1 mw at 0 dbfs 8.9 mw ultra - low power microphone mono record mic_1 to adc_r, 8 khz, quiescent, optimised clocking and bias 0.65 mw note 3 vdd_a=vdd_sp=vdd_io=1.8 v, ta=25c, fs=48 khz, charge pump signal - size mode, 0x95 = 0x06 . table 6 : reference voltage generation parameter description conditions min typ max unit vmid audio mid - rail voltage 0.45 vdd_a v c vmid vmid decoupling capacitor 1.0 f dacref audio dac/adc reference voltage 0.9 vdd_a v c dacref dacref decoupling capacitor 1.0 f vbg bandgap voltage 1.2 v c vbg bandgap decoupling capacitor 1.0 f
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 13 of 129 ? 2015 dialog semiconductor 7 parametric specifications table 7 : analogue to digital c onverter (adc ) parameter description conditions min typ max unit v max full - scale input signal digital output level = 0 dbfs 1.6 vdd_a v pp snr ( note 4 ) signal to noise ratio a - weighted no input selected 90 db thd+n ( note 5 ) total harmonic distortion plus noise - 1 dbfs 44.1 khz slave mode - 85 db - 1 dbfs 32 khz pll mode - 80 db in - band s purious analog input level = 0 dbfs - 85 db channel separation 90 db b pass pass band 0.45*fs hz b stop stop band fs ? 48 khz fs = 88.2/96 khz 0.56*fs 7*fs 3.5*fs hz pass band r ipple voice mode music mode 0.3 0.1 db stop band a ttenuation voice mode music mode 70 55 db group delay voice mode music mode fs = 88.2/96 khz 4.3/fs 18/fs 9/fs s group delay mismatch between left and right channels 2 s psrr ( note 6 ) with respect to vdd_a power supply rejection ratio 20 hz C 2 khz 2 k hz C 20 khz 70 50 db note 4 snr (signal - to - noise ratio) is a ratio of the full - scale output signal level to the noise level with no signal applied . note 5 thd+n (total harmonic distortion plus noise) is a ratio of the level of the harmonics and noise to the output signal . note 6 psrr (power supply rejection ratio) is a measure of the attenuation of a signal on the supply to the signal at the output .
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 14 of 129 ? 2015 dialog semiconductor table 8 : microphone bias micbias1 and micbias2 parameter description conditions min typ max unit v micbias bias v oltage no load, vdd_mic > v micbias + 200 mv 1.52 1.57 1.62 v 2.18 2.25 2.32 2.41 2.48 2.56 2.91 3.00 3.10 i bias maximum c urrent voltage drop < 50 mv 2 ma psrr with respect to vdd_mic power supply rejection r atio 20 hz C 200 hz >2 khz 70 50 db v noise output noise v oltage v micbias 2.2 v 5 v rms capacitive l oad i bias < 100 a 100 a < i bias < 2 ma 100 200 pf
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 15 of 129 ? 2015 dialog semiconductor table 9 : input mixing units (mic1_p/mic1_n/mic2_p/mic2_n/aux_l/aux_r ) to adc_l/adc_r parameter description conditions min typ max unit v max full - scale input signal single - ended differential mic_1/2_amp = aux_l/r_amp = mixin_l/r = 0 db 0.8 vdd_a 1.6 vdd_a v pp r in input resistance mic, single - ended aux 12 6 15 18 40 k? c in input capacitance 1 pf amplitude ripple 20 hz to 20 khz - 0.5 +0.5 db programmable gain mic_1_amp and mic_2_amp aux_l_amp and aux_r_amp mixin_l and mixin_r - 6 - 54 - 4.5 36 15 18 db programmable gain step size mic_1_amp and mic_2_amp aux_l_amp and aux_r_amp mixin_l and mixin_r 6 1.5 1.5 db absolute gain accuracy 0 db @ 1 khz - 1.0 +1.0 db left/right gain mismatch 20 hz to 20 khz - 0.1 +0.1 db gain step error 20 hz to 20 khz - 0.1 +0.1 db input noise level inputs connected to gnd, a - weighted, input - referred, measured @ adc output mic_1/2_amp = 24 db aux_l/r_amp = 15 db 5 6.5 v rms psrr with respect to vdd_a power supply rejection ratio single - ended input 20 hz to 2 khz 20 khz 70 50 db differential input 20 hz C 2 khz 2 k hz C 20 khz 90 70 db
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 16 of 129 ? 2015 dialog semiconductor 8 digital signal processing table 10 : adc/dac d igital high - pass filter cut - off frequencies in music mode sampling f requency (khz) music mode C cut - off f requency ( - 3 db) in hz at adc_audio_hpf _corner / dac_audio_hpf_corner register s ettings 00 01 10 11 8 0.3 0.7 1.3 2.7 11.025 0.4 0.9 1.8 3.7 12 0.5 1 2 4 16 0.7 1.3 2.7 5.3 24 1 2 4 8 32 1.3 2.7 5.3 10.7 44.1 1.8 3.7 7.3 14.7 48 2 4 8 16 88.2 3.6 7.4 14.6 29.4 96 4 8 16 32 table 11 : adc/dac digital high - pass filter cut - off frequencies in voice mode sampling f requency (khz) voice mode C cut - off frequency ( - 3 db) in hz at adc_audio_hpf_corner / dac_audio_hpf_corner register settings 000 001 010 011 100 101 110 111 8 2.66 25 50 100 150 200 300 400 11.025 3.5 35 69 138 207 275 415 553 12 4 37.5 75 150 225 300 450 600 16 5 50 100 200 300 400 600 800
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 17 of 129 ? 2015 dialog semiconductor table 12 : dac 5 - b and equaliser frequencies sampling f requency (khz) centre/cut - off frequency of 5 - band e qualiser (hz) band 1 c ut - off ( note 7 ) band 2 c entre band 3 c entre band 4 c entre band 5 c ut - off ( note 7 ) 8 21 85 563 1151 2909 11.025 29 117 776 2137 4009 12 31 128 845 2326 4364 16 41 90 441 2128 5840 22.05 56 124 607 2933 8048 24 61 135 664 3192 8759 32 58 95 418 1731 6374 44.1 80 132 577 2385 8784 48 87 143 628 2596 9560 88.2 n/a n/a n/a n/a n/a 96 n/a n/a n/a n/a n/a note 7 for equaliser bands 1 and 5 the cut - off frequency depends on the gain setting. the figures quoted in this table refer to the C 1 db point with the band gain set to C 3 db table 13 : beep generator parameter description conditions min typ max unit single - tone frequency 10 12000 hz single - tone frequency step 10 hz dual - tone modulation frequency a 697 770 852 941 hz dual - tone modulation frequency b 1209 1336 1477 1633 hz output signal level 45 0 dbfs output signal step size 3 db t on ,t off on/off pulse duration 10 2000 ms on/off pulse step size t on/off =10 C 200 ms t on/off =200 C 2000 ms 10 50 ms on/off pulse repeat c ontinuous mode 1,2,4,8,16,32 cycles
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 18 of 129 ? 2015 dialog semiconductor 9 audio outputs table 14 : digital to a nalogue c onverter (dac) parameter description conditions min typ max unit v max full - scale output signal digital input level = 0 dbfs 1.6vdd _ a v pp snr signal to noise ratio a - weighted 100 db thd+n total harmonic distortion plus noise - 1 dbfs 44.1 khz slave mode - 90 db - 1 dbfs 32 khz pll mode - 80 db channel separation 90 db b pass pass band 0.45fs khz b stop stop band fs ? 48 khz fs = 88.2/96 khz 0.56fs 7fs 3.5fs khz pass band r ipple voice mode music mode 0.15 0.1 db stop band a ttenuation voice mode music mode 70 55 db group delay voice mode music mode fs = 88.2/96 khz 4.8/fs 18.5/fs 9/fs s group delay variation 20 hz to 20 khz 1 s group delay mismatch between left and right channels 2 s psrr with respect to vdd_a power supply rejection ratio 20 hz C 2 khz 2 k hz C 20 khz 70 50 db
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 19 of 129 ? 2015 dialog semiconductor table 15 : class ab lineout amplifier / speaker from dac_l/dac_r to (sp_p, sp_n) parameter description conditions min typ max unit v max full - scale output signal no load 1.8vdd_ sp v pp p max maximum output power vdd_sp = 1.2 v thd < 10 % r load = 8 ?, 1 khz 65 mw rms vdd_sp = 1.5 v thd < 10 % r load = 8 ?, 1 khz 115 mw rms vdd_sp = 3.7 v thd < 10 % r load = 8 ?, 1 khz 745 mw rms vdd_sp = 5.0 v thd < 10 % r load = 8 ?, 1 khz 1200 mw rms r load load impedance 6.4 8 1 200 h pf frequency response 0.5 db 20 20k hz amplitude ripple 20 hz to 20 khz - 0.5 0.5 db programmable gain - 48 +15 db mute attenuation 100 db programmable gain step size 1 db absolute gain accuracy 0 db @ 1 khz - 0.8 +0.8 db gain step error 20 hz to 20 khz - 0.1 +0.1 db snr signal to noise ratio a - weighted gain = 0 db vdd_sp = 1.6 v 96.5 db v noise output noise l evel non a - weighted gain - 15 db 20 hz to 20 khz 6 v thd+n total harmonic distortion plus noise vdd_sp = 1.6 v - 1 dbfs 44.1 khz slave mode r load > 2 k? - 86 db vdd_sp = 1.6 v - 1 dbfs 32 khz pll mode r load > 2 k? - 80 db psrr with respect to vdd_sp power supply rejection ratio 20 hz C 2 khz 2 k hz C 20 khz 90 70 db
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 20 of 12 9 ? 2015 dialog semiconductor table 16 : true g round charge pump hpcsp and hpcsn parameter description conditions min typ max unit vddcsp positive rail output cp_mod = 11 cp_mod = 10 vdd_a vdd_a / 2 v vddcsn negative rail output cp_mod = 11 cp_mod = 10 - vdd_a - (vdd_a / 2) v flyback capacitor one capacitor 1.0 f reservoir capacitors two capacitors 1.0 f
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 21 of 129 ? 2015 dialog semiconductor table 17 : true g round headphone amplifier from dac_l/dac_r to (hp_l/hp_r) parameter description conditions min typ max unit v max full - scale output s ignal no load 1.6vdd_a v pp dc output offset hp gain < - 30 db 100 v p max maximum power per channel vdd_a = 1.6 v thd < 0.1 % r load =16 , 1 khz l = 23 r = 23 mw rms vdd_a = 1.8 v thd < 0.1 % r load =16 , 1 khz l = 29 r = 29 mw rms vdd_a = 2.5 v thd < 0.1 % r load =16 , 1 khz l = 67 r = 67 mw rms r load l load c load load i mpedance 13 16 400 500 h pf frequency r esponse 0.5 db 20 20k hz amplitude r ipple 20 hz to 20 khz - 0.5 +0.5 db programmable g ain - 56 +6 db mute a ttenuation 70 db programmable gain step s ize 1.0 db absolute gain a ccuracy 0 db @ 1 khz - 0.8 +0.8 db input g ain l/r - m ismatch 20 hz to 20 khz - 0.1 +0.1 db input gain step e rror 20 hz to 20 khz - 0.1 +0.1 db snr signal to noise ratio a - weighted gain = 0 db vdd_a = 2.5 v vdd_a = 1.8 v r load =16 100 98 db v noise output noise l evel 20 to 20 khz, non a - weighted gain < - 20 db 2.5 vrms thd+n total harmonic distortion plus noise vdd_a = 1.6 v - 5 dbfs r load =16 - 87 db psrr with respect to vdd_a power supply rejection ratio 20 hz C 2 khz 2 k hz C 20 khz 70 50 db
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 22 of 129 ? 2015 dialog semiconductor 10 clock generation table 18 : mclk i nput parameter description conditions min typ max unit input a mplitude mclk squarer enabled mclk squarer disabled 0.3 0.9vdd_io vdd_io vdd_io v input i mpedance dc impedance > 10 m 300 0.5 1 2 pf note 8 mclk squarer enabled specification assumes an input frequency of 13 mhz 11 phase locked l oop (pll) table 19 : pll m ode parameter description conditions min typ max unit j a mclk input j itter absolute jitter (rms) ( note 10 ) 5 00 ps f in input frequency normal mode 32 khz mode 2 ( note 9 ) 5 - 50 32.768 50 mhz khz srm tracking r ange dai slave mode wclk frequency variation - 4 4 % srm tracking r ate dai slave mode wclk drift rate 50 ppm/s note 9 see section 13.28 for further details on us ing an mclk frequency between 2 mhz and 5 mhz note 10 jitter in the 100 hz to 40 khz band table 20 : bypass m ode parameter description conditions min typ max unit j a mclk input j itter absolute jitter (rms) ( note 10 ) 500 ps f in input frequency sample frequency: 11.025, 22.05, 44.1, 88.2 khz 8, 12, 16, 24, 32, 48, 96 khz 11.2896 12.288 mhz
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 23 of 129 ? 2015 dialog semiconductor 12 digital interfaces table 21 : i/o c haracteristics parameter description conditions min typ max unit v ih scl, sda, input high v oltage 0.7*vdd_io v v il scl, sda, input low v oltage 0.3*vdd_io v v ih mclk, b clk, wclk, datin, datout input h igh v oltage 0.7*vdd_io v v il mclk, b clk, wclk, datin, datout input low v oltage 0.3*vdd_io v v ol @3 ma sda output low v oltage 0.24 v
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 24 of 129 ? 2015 dialog semiconductor figure 4 : i2c bus t iming table 22 : i2c c ontrol bus ( vdd_io = 1.8 v ) parameter description conditions min typ max unit bus free time stop to start 500 ns bus line capacitive load 150 pf standard/fast mode scl clock frequency 0 1000 khz start condition setup time 260 ns sth start condition hold time 260 ns clkl scl low time 500 ns clkh scl high time 260 ns scl rise/fall time input requirement 1000 ns sda rise/fall time input requirement 300 ns dst sda setup time 50 ns dht sda hold time 0 ns tss stop condition setup time 260 ns high - speed mode scl clock frequency 0 3400 khz start condition setup time 160 ns sth start condition hold time 160 ns clkl scl low time 160 ns clkh scl high time 60 ns scl rise/fall time input requirement 160 ns sda rise/fall time input requirement 160 ns dst sda setup time 10 ns dht sda hold time 0 ns tss stop condition setup time 160 ns s c l s d a s t h c l k l c l k h d s t t s s d h t
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 25 of 129 ? 2015 dialog semiconductor figure 5 : digital audio interface timing diagram note 11 diagram shown is valid for all modes except dsp. for dsp mode the bclk signal is inverted table 23 : digital audio interface t iming (i2s/dsp in master/slave m ode) symbol parameter conditions ( vdd_io = 1.8 v ) min typ max unit input impedance dc impedance > 10 m? 300 1.0 2.5 ? pf t bclk period 75 ns t r bclk rise time 8 ns t f bcl k fall time 8 ns t hc bclk high period 40 % 60 % t t lc bclk low period 40 % 60 % t t dcw bclk to wclk delay - 30 % +30 % t t dcd bclk to datout delay - 30 % +30 % t t hw wclk high time dsp mode 100 % t non - dsp mode word length ( note 12 ) t t lw wclk low time dsp mode 100 % t non - dsp mode word length ( note 13 ) t t sw wclk setup time slave mode 7 ns t hw wclk hold time slave mode 2 ns t sd datin setup time 7 ns t hd datin hold time 2 ns t dwd datout to wclk delay datout is synchronised to bclk note 12 wclk must be high for at least the word length number of bclk periods note 13 wclk must be low for at least the word length number of bclk periods t t l c t h c b c l k d a t i n t f t s d d a t o u t w c l k t r t d c w t d c d t d w d t h d t s w t h w
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 26 of 129 ? 2015 dialog semiconductor 12.1 codec start - up t ime after the audio system controller has been enabled using system_modes_input and system_modes_output, the start - up times for the various codec paths are as specified below: table 24 : codec start - up times source output comment min typ max unit vmid vmid > 90 % of final value 1 f capacitor 25 ms any analogue input or dac_l/r hp_l hp_r pll bypass or pll normal mode 200 200 ms any analogue input or dac_l/r hp_l hp_r pll srm or pll 32 khz mode 500 ms any analogue input or dac_l/r sp_p sp_n pll bypass or pll normal mode 250 ms any analogue input adc_l adc_r pll bypass or pll normal mode 200 ms any analogue input adc_l adc_r pll srm or pll 32 khz mode 600 ms
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 27 of 129 ? 2015 dialog semiconductor 13 functional description 13.1 general description DA7212 is an ultra - low - power audio codec with true ground headphone drivers, mixing capability, and digital audio enhancement. it offers hi - fi audio quality with class - leading power consumption for portable media and embedded applications. featuring a high efficiency headphone amplifier and minimum supply voltage of 1.6 v, the ultra - low 3.1 mw quiescent power consumption extends music playback time for battery - operated equipment. control and data interfaces are supplied from a dedicated vdd_io rail. for compatibility with higher i/o levels, an extended voltage range up to 3.6 v can be se lected. the integrated pll uses a fractional - n architecture that supports frequencies from 2 mhz to 50 mhz. standard mobile phone/usb system clock frequencies are supp orted, and audio data synchronis ation is supported even when no master clock is available. the DA7212 has a stereo pair of single - ended line inputs as well as two microphone inputs, each of which can be configured as single - ended or differential. both line and microphone signals can be routed to the adc or directly to the output mixer s via a bypass path. in addition, the DA7212 supports both single and dual - channel digital microphone inputs by routing the digital signals directly to the adc digital filters. input and output mixers with stereo - to - mono conversion also support mono configurations such as single speaker outputs. three output drivers are available in the output stage of the DA7212 . a stereo true - ground amplifier directly drives standard 3 - wire 16 ohm headphones while a differential mono speaker amplifer is capable of driving 1.2 w into 8 ohms. audio enhancement functions are performed digitally including programmable high - pass filtering, 5 - band eq, noise - gate and an agc with configurable attack and decay parameters. the multislot i2s/pcm digital audio interface (dai) supports all common sample rates between 8 khz and 96 khz in master or slave modes. the codec register space can be accessed via the i2c interface of DA7212 on the default 7 - bit address 0x1a. DA7212 implements a unique smart controller that enables easy co nfiguration of the codec for different application scenarios, thereby reducing the number of register writes needed for each case. the smart controller runs automatically once enabled, and is optimised to allow pop - free and click - free power - up and power - do wn operation .
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 28 of 129 ? 2015 dialog semiconductor 13.2 input signal c hain the DA7212 has a stereo pair of single - ended line inputs as well as two microphone inputs that can each be configured as single - ended or differential. both line and microphone signals can be routed to the adc or directly to the output mixers via a bypass path. in addition, the DA7212 supports both single and dual channel digital microphone inputs by routing the digital signals directly to the adc digital filters. the input routing paths and input amplifier gain ranges are illustrated in figure 6 . figure 6 : audio input routing and gain ranges m i c _ 2 _ a m p - 6 d b t o + 3 6 d b i n 6 d b s t e p s a u x _ l _ a m p m i x i n _ l - 4 . 5 d b t o + 1 8 d b i n 1 . 5 d b s t e p s a u x _ l m i c 2 _ n m i c b i a s 1 m i c 2 _ p a u x _ r m i c b i a s 2 m i c _ 1 _ a m p a u x _ r _ a m p - 5 4 d b t o + 1 5 d b i n 1 . 5 d b s t e p s m i x i n _ r t o a d c _ l t o a d c _ r m i c 1 _ n / d m i c i n m i c 1 _ p / d m i c c l k f r o m p l l t o a d c f i l t e r s - 6 d b t o + 3 6 d b i n 6 d b s t e p s - 5 4 d b t o + 1 5 d b i n 1 . 5 d b s t e p s - 4 . 5 d b t o + 1 8 d b i n 1 . 5 d b s t e p s
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 29 of 129 ? 2015 dialog semiconductor 13.3 microphone i nputs the DA7212 includes two pairs of analogue microphone inputs that can be connected in three ways: fully differential mode for improved common mode noise rejection single ended or pseudo - differential mode by connecting mic1_n or mic2_n to gnd (see figure 7 ). the microphone source is specified using mic_1_amp_in_sel and mic_2_amp_in_sel single ended or pseudo - differential mode by connecting mic1_p or mic2_p to gnd (see figure 7 ). the microphone source is specified using mic_1_amp_in_sel and mic_2_amp_in_sel the microphone pgas are enabled by the mic_1_amp_en / mic_2_amp_en controls and can be muted via mic_1_amp_mute_en / mic_2_amp_mute_en . for maximum flexibility, each microphone channel includes an ind ividual gain setting ( mic_1_amp_gain / mic_2_amp_gain controls) that has a range of - 6 db to +36 db in 6 db steps. the currently active gain setting of each microphone is stored in mic_1_gain_status and mic_2_gain_status. a maximum analogue gain from microphone to adc input of +54 db with a resolutio n of 1.5 db can be selected. figure 7 : typical microphone application for mic1 (mic2 is similar) standard electret microphones can be supplied from an embedded microphone bias regulator, enabled using the micbias2_en control bit. two separate outpu ts are available on either the micbias1 pin or the micbias2 pin. these are enabled using the micbias2_en and micbias1_en controls. the voltage on the micbias pins is set to 1.6 v, 2.2 v, 2.5 v or 3.0 v by the micbias2_level and micbias1_level controls. the microphone bias generates an ultra - low - noise voltage to feed several electret microphones with up to 2 ma. 13.4 digital microphones DA7212 implements a digital microphone interface via a clock output (shared pin with mic1_p) and a serial data input (shared pin with mic1_n). the serial data is a sigma delta sampled bitstream. modulators up to 3rd order are supported. micbias1 can be used to power the digital microphone, but it must be enabled because it is micbias1 that supplies the digital microphone pins. the clock and data pins are shared with two a nalogue microphone inputs. this allows DA7212 to record from single or dual channel digital microphones, or from conventional mono/stereo analogue microphones. the clock frequency can be selected to be either 1.5 mhz or 3 mhz by using dmic_clk_rate control . m i c b i a s 2 m i c 1 _ n ( c ) s i n g l e - e n d e d m i c b i a s 1 m i c 1 _ p ( c ) s i n g l e - e n d e d m i c b i a s 1 m i c 1 _ p m i c 1 _ n ( b ) p s e u d o - d i f f e r e n t i a l m i c b i a s 1 m i c 1 _ p m i c 1 _ n ( a ) d i f f e r e n t i a l
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 30 of 129 ? 2015 dialog semiconductor single channel and dual channel digital microphone modules are supported. the dual channel modules change the output data on both the rising and the falling edges of the clock, as illustrated in figure 7. in this case dmic_samplephase must be set to zero in order to enable the sample detection at the edges of the clock. each dmic input is enabled via dmic_l_en / dmic_r_en and is associated with a clock edge via dmic_data_sel control. a digital microphone requires a decimation filter to reconstruct the sig nal at the required sampling rate. the adc decimation filters are re - used for this purpose, so either digital microphones or analogue sources may be used for recording at any one time. figure 8 : digital microphone timing example 13.5 auxiliary inputs standard analogue sources (for example fm radio) are supported via the aux stereo line inputs. auxiliary inputs are enabled by aux_l_amp_en / aux_r_amp_en . they can be summed with each other, and with the microphone paths, which enables flexible audio mixing. each channel includes individual gain settings in 1.5 db steps from - 54 db to +15 db using aux_l_amp_gain and aux_r_amp_gain . the auxiliary amplifiers can be muted by asserting aux_l_amp_mute_en and aux_r_amp_mute_en. changes in gain can be synchronised with zero - crossing by asserting the aux_l_amp_zc_en and aux_r_amp_zc_en bits. if no zero - crossing is detected within approximately 85 ms, the gain change is applied unconditionally. the sensitivit y of the zero - cross detector is maximised by automatic selection of whether the zero - cross detection is performed at the input to the aux amplifier, or the output from it. this is configured using the aux_l_amp_zc_sel and aux_r_amp_zc_sel controls. smooth changes in gain are enabled by asserting the aux_l_amp_ramp_en and aux_r_amp_ramp_en controls. if the ramp controls are asserted, the rate of ramping is specified by the gain_ramp_rate control. any zero - cross activation is over - ridden if gain ramping is set. the currently active aux_l_gain and aux_r_gain settings are stored in the aux_l_gain_status and aux_r_gain_status controls. d m i c c l k o u t p u t 1 t o d m i c 1 o u t p u t 2 t o d m i c 1 d a t a v a l i d f a l l i n g e d g e t o v a l i d d a t a o n 1 f a l l i n g e d g e t o h i g h i m p e d a n c e o n 2 r i s i n g e d g e t o v a l i d d a t a o n 2 r i s i n g e d g e t o h i g h i m p e d a n c e o n 1 d a t a v a l i d d a t a h i g h z d a t a v a l i d d a t a h i g h z d a t a h i g h z
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 31 of 129 ? 2015 dialog semiconductor 13.6 input mixers the da7 212 has two second level input amplifiers (mixin_l and mixin_r) that mix the analogue inputs as well as providing up to 18 db extra gain. they are enabled by asserting the controls mixin_l_amp_en and mixin_r_amp_en. gain can be controlled in 1.5 db steps f rom 4.5 db to +18 db using the mixin_l_gain and mixin_r_gain register bits. zero - crossing can be enabled by asserting mixin_l_amp_zc_en or mixin_r_amp_zc_en. if no zero crossing is detected within approximately 85 ms, the gain change is applied uncondition ally. smooth changes in gain are performed by asserting the mixin_l_amp_ramp_en and mixin_r_amp_ramp_en controls. if the ramp controls are asserted, the rate of ramping is specified by the gain_ramp_rate control. any zero - cross activation is over - ridden if gain ramping is set. the left mixer accepts inputs from aux_l_amp and from either or both of the microphone pgas (mic_1_amp and mic_2_amp), as well as from the right mixer mixin_r for stereo - to - mono conversion. similarly the right m i xer accepts inputs fro m aux_r_amp and from either or both of the microphone pgas (mic_1_amp and mic_2_amp), as well as from the left mixer mixin_l for stereo - to - mono conversion. input channel selection is determined by mixin_l_mix_select and mixin_r_mix_select. the mixers can b e muted using the mixin_l_amp_mute_en and mixin_r_amp_mute_en controls. the currently active gain settings are stored in mixin_l_amp_gain_status and mixin_r_amp_gain_status registers. 13.7 stereo audio adc DA7212 includes a low power 24 - bit high quality audio adc that supports sampling rates from 8 khz to 96 khz. the sample rate is specified using the sr register. the adc can be enabled and disabled on either channel using adc_l_en and adc_r_en, thereby providing the opportunity to save power during mono opera tion. the adc channels offer a configurable digital gain from - 83.25 db to +12 db in 0.75 db steps after the digital conversion. individual gain settings can be programmed via controls adc_l_digital_gain _status and adc_r_digital_gain _status . the currently active gain settings are stored in adc_l_gain_status and adc_r_gain_status registers. muting, and the ramping of digital gain changes, can be controlled using the dedicated adc_l_ctrl and adc_r_ctrl registers. if the ramping is enabled using the control bits adc_l_ramp_en and adc_r_ramp en, the rate of the ramping is controlled using gain_r amp_rate. to enable saturation - free signals with maximum signal to noise ratios, the input levels of the adc are adjusted with second level pgas that are enabled with controls mixin_l_amp_en and mixin_r_amp_en. the signal routing and mix are configured us ing the mixin_l_select and mixin_r_select registers. on the dedicated mixin_l_ctrl and mixin_r_ctrl registers, settings such as gain changes at zero - cross (for smooth volume changes), ramping of gain changes at signal zero cross ramping of gain changes, a nd mute can be configured. if the ramping is enabled using the control bits mixin_l_amp_ramp_en and mixin_r_amp_ramp_en, the speed of the ramp can be configured on gain_ramp_rate.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 32 of 129 ? 2015 dialog semiconductor 13.8 au tomatic level c ontrol (alc) for improved sound recordings of signals wit h a large volume range, the DA7212 offers a fully - configurable automatic recording level control (alc) for microphone inputs. this is enabled via the alc_l_en and alc_r_en controls, and can be enabled independently on either left or right channel. it is re commended that the alc is only enabled in stereo as this applies the same gain to both channels and so protects the pan of stereo signals. the alc monitors the digital signal after the adc and adjusts the microphones analogue and digital gain to maintain a constant recording level, whatever the analogue input signal level. operation of alc is illustrated in figure 9 . when the input signal volume is high, the alc system will reduce the overall gain until the output volume is below the specified maximum value. when the input signal volume is low, the alc will increase the gain until the output volume increases above the specified minimum value. if the output signal is within the desired signal level (between the specified minimum and maximum levels), the alc does nothing. the maximum and the minimum thresholds that trigger a gain change of the alc are programmed by the alc_threshold_max and alc_threshol d_min controls. figure 9 : principle of o peration of the alc the total gain is made up of an analogue gain, which is applied to the microphone pgas, and a digital gain, which is implemented in the filte ring stage. the alc block monitors and controls the gain of the microphone pgas and the adc. note that although the alc is controlling the gain, it does not modify any of the registers mic_1_amp_gain, mic_2_amp_gain, adc_l_digital_gain and adc_r_digital_ga in. these registers are ignored while the alc is in operation. the minimum and maximum levels of digital gain that can be applied by the alc are controlled using alc_atten_max and alc_gain_max . similarly the minimum and maximum levels of analogue gain are controlled by alc_ana_gain_min and alc_ana_gain_max . the rates at which the gain is changed are defined by the attack and decay rates in register alc_ctrl2. when attacking, the gain decreases with alc_attack rate. when decaying, the gain increases with alc_release rate. the hold - time is defined by alc_hold in the alc_ctrl3 register. this controls the length of time that the system maintains the current gain level before starting to decay. this prevents unwanted changes in the recording level when there i s a short - lived spike in input volume, for example when recording speech. typically the attack rate should be much faster than the decay rate, as it is necessary to reduce rapidly increasing waveforms as quickly as possible, whereas fast release times w ill result in the a l c i n p u t a l c g a i n a l c o u t p u t a l c m a x l e v e l a l c m i n l e v e l r e l e a s e t i m e a t t a c k t i m e
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 33 of 129 ? 2015 dialog semiconductor signal appearing to pump. the alc also has an anti - clipping function that applies a very fast attack rate when the input signal is close to full - range. this prevents clipping of the signal by reducing the signal gain at a faster rate th an would normally be applied. the anti - clip function is enabled using alc_anticlip_en, and the threshold above which it is activated is set in the range 1/128 full - scale to full - scale using alc_anticlip_level. a recording noise - gate feature is provided to avoid increasing the gain of the channel when there is no signal, or when only a noise signal is present. boosting a signal on which only noise is present is known as noise pumping. the noise - gate prevents this. whenever the level of the input signal dro ps below the noise threshold configured in alc_noise , the channel gain remains constant. figure 10 : attack, delay and h old parameters m a x m i n a t k d c y h l d i n p u t s i g n a l g a i n l e v e l a t k r a t e d c y r a t e t i m e t i m e
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 34 of 129 ? 2015 dialog semiconductor 13.9 beep generator and c ontroller the DA7212 has two sine wave generators (swg). each swg can generate an audio frequency from 10 hz to 12 khz with a 12.288 mhz system clock (or from 10 hz to 11.02 khz with a 11.288 mhz system clock). the output frequency of each swg can be specified with a 10hz step size using the freq1_l and freq1_u registers for swg 1, and freq2_l and freq2_u for swg 2. for all output frequency calculations, freq[15:8] = freqn_u freq[7:0] = freqn_l for sample rates (sr) = 8/12/16/24/32/48/96 khz, freq = (2^16 * (f hz /12)) - 1 for sample rates (sr) = 11.025/22.05/44.4/88.2 khz, freq = (2^16 * (f hz /11.025)) - 1 the swgs have a programmable gain that can be set in 3 db steps from 0 db to 45 db using the gain register field. the gain setting applies equally to both swgs. the beep genera tor generates beeps that can be a single tone from either swg (register swg_sel = 1 or swg_sel = 2), or a mix of two tones from the two swgs (register swg_sel = 0 or swg_sel = 3). the beep generator can also output standard dtmf keypad values (listed in ta ble 4) by asserting the dtmf_en register bit. note that output from the beep generator is mixed into the dai to dac path. this means that if the source path for dac_l or dac_r is selected to be adc_l or adc_r (registers 0x2a[5:4] and 0x2a[1:0]), the beep g enerator is omitted from t he signal path. table 25 : dtmf k eypad frequencies frequency 1 (hz) frequency 2 (hz) 697 770 852 941 1209 1 2 3 a 1336 4 5 6 b 1477 7 8 9 c 1633 * 0 # d the beep tone on and off periods are specified using the beep_on_per and beep_off_per register fields. beep - on and beep - off periods can be configured in 10 ms steps from 10ms to 200 ms, and in 50 ms steps from 250 ms to 2000 ms. the beep - on period can also be configured as continuous. the number of bee p cycles is configured using the beep_cycles register field. the tone generator is started by asserting the start_stopn register bit, and is halted by clearing it. if start_stopn is cleared, beep generation terminates on completion of the current beep - cycl e, or at the next zero - cross if in continuous mode. the start_stopn register bit is cleared automatically once the programmed number of beeps has completed. in continuous - beep mode (beep_cycles = 6 or 7, or beep_on_per = 63), the tone generator is switched off by clearing start_stopn.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 35 of 129 ? 2015 dialog semiconductor 13.10 output signal c hain the DA7212 has two audio outputs. these are a stereo class - g headphone driver, and a mono class - ab speaker driver. two output mixers allow mixing of signals from the dacs and the analogue bypass paths, wi th output going to any or all of the three output pgas. these output paths are illustrated in figure 11 . figure 11 : analogue output signal paths and gain ranges 13.11 stereo a udio dac the integrated stereo dac is suitable for high quality audio p layback by mp 3 players and by portable multi media players of all kinds. the left and right channels of the dac can be individually enabled using controls dac_l_en and dac_r_en. each channel includes individual gain settings that are controllable in 0.75 d b steps from - 78 db to 12 db using dac_l_digital_gain _status and dac_r_digital_gain _status . the currently active gain settings are stored in dac_l_gain_status and dac_r_gain_status registers. on the dedicated dac_l_ctrl and dac_r_ctrl registers, settings s uch as mute and ramping of gain changes can be configured. if ramping is enabled using the control bits dac_l_ramp_en or dac_r_ramp_en, the rate of the ramping can be controlled using gain_ramp_rate. a digital high - pass filter for each dac channel is impl emented with a 3 db cut - off frequency controlled by dac_audio_hpf_corner. the high - pass filter is enabled by control dac_hpf_en. after reset, the high pass filters for both channels are enabled by default. f r o m d a c _ l f r o m a u x _ l _ a m p f r o m m i x i n _ l f r o m d a c _ r f r o m m i x i n _ r h p _ l h p _ r s p _ p s p _ n h p _ l _ a m p h p _ r _ a m p - 5 7 d b t o + 6 d b i n 1 d b s t e p s f r o m a u x _ r _ a m p - 4 8 d b t o + 1 5 d b i n 1 d b s t e p s l i n e _ a m p - 5 7 d b t o + 6 d b i n 1 d b s t e p s
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 36 of 129 ? 2015 dialog semiconductor 13.12 output m ixer for playback, the output mixer ampl ifier is enabled using mixout_l_amp_en and mixout_r_amp_en. the audio signal can be mixed from all sources, and can be output simultaneously to both headphones and speakers. the mixing takes place only after asserting the control mixout_l_mix_en and mixout _r_mix_en. the output mixer is configured using register mixout_l_select and mixout_r_select. this output - mixer control is independent of the input path, so recording of one audio signal while listening to another signal such as fm radio or an mp3 file is possible. the playback sound can be mixed with background signals or with inverted background microphone signals (side tone) to enable a basic headphone environmental noise reduction, or to compensate for unwanted damping of environmental sound while list ening with sealed headphones. playback signals coming from the aux or microphone input channels can be individually inverted before being mixed out to the left and right channel (see mixout_l_select and mixout_r_select registers). a stereo to mono conversi on can be implemented by using either the input or the output mixer. this allows direct feeding of high power speaker amplifiers and other mono devices with the complete audio content. 13.13 headphone a mplifier the headphone class g amplifiers offer 'true ground ' technology, which allows cost and space optimisation by removing the need for bulky headphone - coupling capacitors. this also enhances the bass performance, which is typically reduced by conventional ac - coupling. in comparison to alternative approaches li ke phantom ground, true ground technology generates real ground - centred output signals, which provide common gnd as required for mini - usb connectors and cea 936 a - compliant interfaces. an embedded offset compensation circuit suppresses click and pop no ise during start - up and dynamic supply voltage adjustments. integrated short circuit protection enables a resistors free connection to a standard audio jack, to achieve a maximum output power of up to 67 mw per channel (referenced to vdd_a ). headphone lo ad impedance is typically 16 , but the paths can also be used as volume controlled lineout signals for external speaker amplifiers and audio devices. the headphone class g amplifiers are supplied from the positive vdd_a rail via a capacitive charge pump t hat generates the negative rail required for true ground mode. for improved power efficiency, the headphone headphone supply voltage levels are dynamically adjusted between vdd_a and vdd_a /2 to match the levels of the left and right headphone signals . the headphone amplifiers are enabled with controls hp_l_amp_en and hp_r_amp_en. for optimum pop and click performance when switching the amplifier on and off, the headphone amplifier provides a high impedance mode that can be enabled via hp_l_amp_oe / hp _r_amp_oe. balance is controlled by programming the left and right gains separately. the gain of each headphone channel can be programmed independently in steps of 1.0 db from +6 db down to C 57 db using controls hp_l_amp_gain / hp_r_amp_gain. settings suc h as mute, gain changes at signal zero cross (for smooth volume changes), and the ramping of gain changes are controlled using the dedicated hp_l_ctrl and hp_r_ctrl registers. if the ramping is enabled using the control bits hp_l_amp_ramp_en and hp_r_amp_r amp_en, the rate of the ramping is controlled using gain_ramp_rate. for smooth volume changes, the gain update can be synchronised to audio signal zero - crossings using hp_l_amp_zc_en and hp_r_amp_zc_en. if no zero crossing is detected within approximately 85 ms, the gain change is applied unconditionally. the left and right channels are synchronised independently.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 37 of 129 ? 2015 dialog semiconductor 13.14 speaker a mplifier the differential lineout channel can be used to directly drive mini speakers with a nominal impedance 8 . for highest efficiency and speaker output power, a direct supply from the battery is supported via a separate supply pin. this amplifier offers individually programmable volume control in 1.0 db steps from +15 db to 48 db using line_amp_gain. on the dedicated line_ctr l register, settings such as mute, tri - state output mode and ramping of gain changes can be configured. if ramping is enabled via control bit line_amp_ramp_en, the rate of the ramping can be configured on gain_ramp_rate. the differential speaker amplifier can be used to drive mini - speakers with an impedance of 8 or higher. a direct supply from the battery is provided by the vdd_sp pin. th is allows maximum speaker power and a wide operating range from 5.0 v down to 1.0 v. the mono lineout/speaker amplifier is enabled by asserting line_amp_en. gain can be set in the range - 48 db to +15 db in 1 db steps using the line_amp_gain control. the speaker amplifier can be muted by asserting line_amp_mute_en. smooth updates to line/speaker amplifer gain can be made by asserting line_amp_ramp_en. when line_amp_ramp_en is asserted, gain updates are made by ramping sequentially through all intermediate gain values. if the speaker output is not used then vdd_sp can be left unconnected. 13.15 charge pump c ontrol the charge pump is enabled by asserting cp_en in the cp_ctrl (0x47) register. once enabled, the charge pump can be controlled manually or automatically. when under manual control (cp_mchange = 00), the output voltage level is directly determined by cp_mod. the amount of c harge stored, and therefore the voltage generated, by the charge pump is controlled by the charge pump controller (cp_ctrl register). as the power consumed by devices such as amplifiers is proportional to voltage2, significant power savings are available b y matching the charge pumps output with the systems power requirement. under automatic control, there are three modes of operation that are determined by the cp_mchange setting. all four modes (one manual and three autom atic) are described in table 26 . table 26 : charge pump output voltage control charge pump tracking m ode cp_mchange charge pump output v oltage details 00 manual the charge pumps output voltage is determined by the settings of cp_mod. 01 voltage level depends on the programmed gain setting the charge pump controller monitors the pga volume settings, and generates the minimum voltage that is high enough to drive a full - scale signal at the current gain level. 10 voltage level depends on the dac signal envelope the charge pump controller monitors the dac signal, and generates a voltage that is high enough to drive a full - scale output at the current dac signal volume level 11 voltage level depends on the signal magnitude and the programmed gain setting the charge pump monitors both the programmed volume settings and the actual signal size, and generates the appropriate output voltage. this is the most power - efficient mode of operation. when cp_mchange is set to 10 (tracking dac signal size, described in table 26 ) or cp_mchange is set to 11 (tracking the output signal size), the charge pump switches its supply between the vdd_a rail and the vdd_a /2 rail depending on its power requirements.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 38 of 129 ? 2015 dialog semiconductor when low output voltages are needed, the charge pump saves power by using the lower - voltage vdd_a /2 rail. the switching point between using the vdd_a rail and the vdd_a /2 rail is determined by the cp_thresh_vdd2 register setting. the switching points determined by cp_thresh_vdd2 vary between the two cp_mchange modes, and are summarised in table 27 and table 28 . w hen the charge pump output voltage is controlled manually (cp_mchange = 00) or when it is tracking the pga gain settings (cp_mchange = 01), the charge pump always takes its supply from vdd_ cp . table 27 : cp_thresh_vdd2 s ettings in dac_vol mode (cp_mchange = 10) cp_thresh_vdd2 s etting approximate switching p oint ( note 14 ) notes 0x01 - 30 dbfs do not use. very power - inefficient as nearly always vdd/1 0x03 - 24 dbfs not recommended. very power - inefficient as nearly always vdd/1 0x07 - 18 dbfs good to use but not power efficient 0x0e - 12 dbfs good to use 0x10 - 10 dbfs recommended setting 0x3f C 0x13 not recommended table 28 : cp_thresh_vdd2 settings in signal s ize mode (cp_mchange = 11) cp_thresh_vdd2 s etting approximate switching p oint ( note 14 ) notes 0x00 never not recommended. always vdd/1 mode 0x01 never not recommended. always vdd/1 mode 0x02 - 32 dbfs not recommended. very power - inefficient as nearly always vdd/1 0x03 - 24 dbfs good to use 0x04 - 20 dbfs good to use 0x05 - 17 dbfs good to use 0x06 - 15 dbfs recommended setting 0x07 - 13 dbfs good to use 0x08 - 12 dbfs good to use 0x09 - 11 dbfs good to use 0x0a - 10 dbfs good to use 0x0b - 9 dbfs not recommended. vdd/2 begins to clip 0x0c never not recommended. always vdd/2 mode 0x0d never not recommended. always vdd/2 mode 0x0e never not recommended. always vdd/2 mode 0x0f never not recommended. always vdd/2 mode note 14 full scale (fs) = 1.6 * vdd_a
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 39 of 129 ? 2015 dialog semiconductor 13.16 charge pump clock control the charge pump on DA7212 requires two clocks (cp_clk and cp_clk2). the cp_clk2 clock runs at a slower frequency than cp_clk. it is cp_clk that actually clocks the charge pump. to prevent the clocks stopping in an unknown state, there are always two pulses on cp_clk for every one pulse of cp_clk2. this is illustrated in figure 12 . figure 12 : input (clk) and output c locks (cp_clk and cp_clk2) at cp_fcontrol = 010 when cp_analogue_lvl = 00 (no feedback C see section 13.17 for more details), the charge pumps nominal clock rate cp_clk is controlled by cp_fcontrol, providing a range from 1 mhz (cp_fcontrol = 000) down to 63 khz (cp_fcontrol = 100). with the slower clo ck rates, quiescent power consumption is lower but the trade - off is a reduced load current, and slower changes to the voltage. section 13.17 describ es how quiescent power and load current can be varied according to demand. 13.17 boosting the charge pump using demand feedback control when cp_analogue_lvl = 00, the clock frequency for the charge pump is under direct control of the registers as described in table 29 . when cp_analogue_lvl = 01 or 10 (11 is reserved and is not used), the demands on the charge pump output are tracked, and the clock frequency is boosted when necessary to give the required output current. this gives the benefit of a very low (or even zero) quiescent current when the charge pump is not required combined with a maximum output when that is required. 13.17.1 tracking the demands on the char ge pump output there are three points at which the demands on the charge pump can be tracked. these tracking points are determined by cp_mchange. 13.17.1.1 cp_mchange = 00 (manual mode) if cp_mchange = 00, the voltage level is controlled by the cp_mod setting. 13.17.1.2 cp_mc hange = 01 (tracking the pga gain setting) if cp_mchange = 01, it is the pga gain setting that is tracked, and which provides the feedback to boost the clock frequency when necessary. 13.17.1.3 cp_mchange = 10 (tracking the dac signal setting) if cp_mchange = 01, it is the size of the dac signal that is tracked, and which provides the feedback to boost the clock frequency when necessary. 13.17.1.4 cp_mchange = 11 (tracking the output signal magnitude) if cp_mchange = 01, it is the magnitude of the output signal that is tracked , and which provides the feedback to boost the clock frequency when necessary. c p _ c l k c l k c p _ c l k 2
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 40 of 129 ? 2015 dialog semiconductor 13.17.2 specifying clock frequencies when tracking the charge pump output demand cp_fcontrol specifies the frequency of the charge pump clock. the frequency is fixed and is set manually if cp_mchange = 00 (see section 13.17.1.1 ). the available frequency settings are 1 mhz (the absolute maximum), and 500, 250, 125 and 63 khz. if cp _mchange not = 00, the charge pump load is monitored and the clock frequency adjusted accordingly to allow the charge pump to supply the required current. clock frequency varies depending on the charge pump requirements, and the cp_fcontrol settings specif y the minimum frequency at which the clock will run. the maximum frequency is always 1 mhz. in addition to the cp_fcontrol settings outlined above, and which specify the minimum clock frequency, there is an extra setting of cp_fcontrol = 101 which has no m inimum frequency. the clock frequency is under the complete control of the tracking and feedback mechanism. the frequency can vary from 0 hz when there is no load on the charge pump and no component leakage, up to the maximum of 1 mhz. these settings are a ll summarised in table 29 . 13.17.3 controlling the boost of the charge pump clock - frequency the manner in which the charge pump clock - frequency is boosted is controlled by cp_analogue_lvl. if cp_analogue_lvl = 00, there is no feedback to the clock generator, and the frequency remains fixed at the frequency specified by cp_fcontrol. 13.17.3.1 cp_analogue_lvl = 01 if cp_analogue_lvl = 01, the clock frequency is boosted fro m the base frequency specified in cp_fcontrol by the insertion of extra clock pulses in to the clock signal as and when required. when no extra pulses are being inserted, the clock frequency remains fixed at the value specified by cp_fcontrol. the extra cl ock pulses are inserted in to the clock signal as needed as long as the clock frequency does n ot exceed its maximum of 1 mhz. 13.17.3.2 cp_analogue_lvl = 10 if cp_analogue_lvl = 10, instead of boosting the clock frequency by inserting extra clock pulses as described in section 13.17.3.1 , the clock is restarted. by restarting the clock before the next pulse is due, the frequency is effectively increased. the clock frequency can be increased from the minimum frequency specified in cp_fcontrol, up to the maximum frequency of 1 mhz. these se ttings are all summarised in table 27 .
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 41 of 129 ? 2015 dialog semiconductor table 29 : charge pump current load control cp_analogue_lvl (0x47[1:0]) 00 no current boost 01 variable current boost ( note 15 ) 10 variable current boost ( note 15 ) 11 cp_fcontrol (0x96[2:0]) 000 1 mhz 1 mhz 1 mhz reserved 001 500 khz from 500 khz to1 mhz depending on demand from 500 khz to1 mhz depending on demand reserved 010 250 khz from 250 khz to1 mhz depending on demand from 250 khz to1 mhz depending on demand reserved 011 125 khz from 125 khz to1 mhz depending on demand from 125 khz to1 mhz depending on demand reserved 100 63 khz from 63 khz to1 mhz depending on demand from 63 khz to1 mhz depending on demand reserved 101 reserved 0 hz to 1 mhz depending on dem and 0 hz to 1 mhz depending on demand reserved 110 reserved reserved reserved reserved 111 reserved reserved reserved reserved note 15 power demand is determined bythe pga gain level if cp_mchange = 01, by the dac signal level if cp_mchange = 10 , or by the output signal level if cp_mchange = 11 13.18 other charge pump c ontrols when a higher charge pump output voltage is needed, the charge pump increases its output as the fastest rate possibl e given the controls and settings in that currently in place. once the higher output voltage is no longer needed, the charge pump controller waits for a period determined by the cp_tau_delay setting before reducing the output voltage. for best performance dialog recommend setting cp_tau_delay to 16 ms or greater. the charge pump limiter is controlled by cp_on_off. the limiter restricts the current flow to the charge pumps capacitors at start - up. cp_small_switch_freq_en enables a low - load, low - power switchi ng mode. if cp_small_switch_freq_en is enabled and cp_fcontrol is set to a value between 000 and 100, any feedback from the analogue level detector results in a switch from low - power to full - power. full - power is maintained for one cp_tau_delay period after the pulse. any subsequent pulses restart the cp_tau_delay period. if cp_fcontrol = 101, the first feedback from the analogue level detector primes the change to full - power mode. if another pulse occurs within 32 clock cycles of the first feedback fro m the analogue level detector, full power is enabled for one cp_tau_delay period.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 42 of 129 ? 2015 dialog semiconductor 13.19 digital signal processing e ngine the digital signal processing engine includes a configurable audio processor that offers flexible routing and extensive audio enhancement a nd effects. linear phase fir filters perform the dac interpolation and decimation for the required sample rates. configurable high - pass filtering (optionally enabled on both adc and dac) removes any signal dc offset and can help to filter out wind noise. a 5 - band playback equaliser can be configured to suit the users listening preferences. 13.20 variable high - pass audio f ilter (dc cut) any dc offset from the input path is removed via iir filters (typically <2 hz roll - off, configurable). after reset the filters f or both channels are enabled by default, but can be disabled by clearing adc_hpf_en and dac_hpf_en. the cut - off frequency of the filters can be programmed using adc_audio_hpf_corner and dac_audio_hpf_corner. enabling the high pass filter is especially impo rtant if the adc output is fed into the dac. table 30 : adc/dac digital high - pass filter specifications in audio m ode sampling f requency (khz) cut - off frequency (hz) at adc_audio_hpf_corner and da c_audio_hpf_corner s ettings 00 01 10 11 8 0.3 0.7 1.3 2.7 11.025 0.4 0.9 1.8 3.7 12 0.5 1 2 4 16 0.7 1.3 2.7 5.3 22.05 0.9 1.8 3.7 7.3 24 1 2 4 8 32 1.3 2.7 5.3 10.7 44.1 1.8 3.7 7.3 14.7 48 2 4 8 16 figure 13 : adc and dac dc blocking (cut - off frequency setting 00 to 11, 16 khz)
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 43 of 129 ? 2015 dialog semiconductor 13.21 variable high pass filter (wind noise f iltering) to improve the quality of microphone recordings, the DA7212 provides a programmable high pass filter engine, enabled via adc_voice_en in the adc_filters1 register . f or the first filter, in music mode adc_voice_en must be set to 0 and the hpf corner frequency is set using adc_audio_hpf_corner. in adc voice mode, adc_voice_en must = 1 and adc _hpf_en must = 1 i n which case the hpf corner frequency is set using adc_voice_hpf_corner. the low frequency roll off is configured over a wide range using the adc_voice_hpf_corner control. this allows for flexible removal of wind and pop noise. during playback, dedicated voiceband filtering can be enabled using dac_voice_e n. in dac voice mode, dac_voice_en must = 1 and dac _hpf_en must = 1 in which case the hpf corner frequency is set using dac_voice_hpf_corner. the low frequency roll off is configured over a wide range using the dac_voice_hpf_corner control. in v oice mode, the wind noise high - pass filter cut - off frequency is determined by the settings of the adc_voice_hpf_corner and the dac_voice_hpf_corner register bits, these cut - off frequencies are not fixed, however, and vary with the sample rate being used. table 31 shows the cut - off frequencies for all valid settings of adc_voice_hpf_corner and dac_voice_hpf_corner, at all sample rates of 16 khz and below. table 31 : wind noise high - pass filter specifications cut - off frequency at adc_voice_hpf_corner and dac_voice_hpf_corner settings ( voice filtering only, and with sample r ate 16 khz or lower) fs [khz] 000 001 010 011 100 101 110 111 8.0 2.5 25 50 100 150 200 300 400 11.025 3.4 34.5 69 138 207 276 413 551 12.0 3.75 37.5 75 150 225 300 450 600 16.0 5 50 100 200 300 400 600 800 figure 14 : wind noise high - pass filter (cut - off frequency setting 000 to 111, 16 khz)
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 44 of 129 ? 2015 dialog semiconductor 13.22 dac 5 - band e qualiser to enable user controllable listening preferences, the digital playback path includes a programmable 5 band equaliser that is enabled by control dac_eq_en. a low pass filter, a three band - pass filters and a high pass fi lter with cut - off/centre frequencies at approximately 87 hz, 132 hz, 628 hz, 2.6 khz and 9.6 khz (for fs=48 khz) offer boosting or damping of each frequency band in 1.5 db steps from 10.5 to +12 db. the gains of each band can be individually configured usi ng dac_eq_band1, dac_eq_band2, dac_eq_band3, dac_eq_band4, dac_eq_band5 controls. the 5 - band equaliser cannot be used at 88.2 and 96 khz sampling rate. for frequency responses see table 32 , and figure 15 to figure 19 . table 32 : dac 5 - band equaliser turnover/centre f requencies sampling f requency (khz) cen tre/cut - off frequency of dac 5 - band e qualiser (hz) band 1 c ut - off ( note 16 ) band 2 c ut - off band 3 c ut - off band 4 c ut - off band 5 c ut - off ( note 16 ) 8 21 85 563 1151 2909 11.025 29 117 776 2137 4009 12 31 128 845 2326 4364 16 41 90 441 2128 5840 22.05 56 124 607 2933 8048 24 61 135 664 3192 8759 32 58 95 418 1731 6374 44.1 80 132 577 2385 8784 48 87 143 628 2596 9560 88.2 n/a n/a n/a n/a n/a 96 n/a n/a n/a n/a n/a note 16 for equaliser bands 1 and 5, the cut - off frequency depends on the gain setting. the figures quoted in this table refer to the C 1 db point with the band gain set to C 3 db figure 15 : equaliser filter b and 1 frequency response at fs = 48 khz
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 45 of 129 ? 2015 dialog semiconductor figure 1 6 : equaliser filter b and 2 frequency response at fs = 48 khz figure 17 : equaliser filter b and 3 frequency response at fs = 48 khz figure 18 : equaliser filter b and 4 frequency response at fs = 48 khz
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 46 of 129 ? 2015 dialog semiconductor figure 19 : equaliser filter b and 5 frequency response at fs = 48 khz 13.23 soft m ute to improve the users perception of audio reconfigurations, t he dac channel signals may be soft muted by asserting the control dac_softmute_en. the soft mute function attenuates the digital input to the dac, ramping the gain down in steps of 0.1875 db from its current level to - 77.25 db, then completely muting the c hannel. when dac_softmute_en is released, the attenuation is set to 77.25 db, and then ramped up to the previous gain level. both left and right channels of soft mute enabled output amplifiers are muted simultaneously. the ramping up and down rate is depen dent on the audio sample rate and can be individually configured using control dac_softmute_rate. d uring active soft muting, the digital gain of the dac will be different to the value programmed inside controls dac_l_digital_gain _status and dac_r_digital_g ain _status . 13.24 playback noise - g ate noise - g ate is an automatic gain control for dac playback that reduces the noise heard during playback if no signal is present. it is enabled using the dac_ng_en control. when the output signals on both channels are below a g iven threshold level, and they stay low for longer than a specified period, then playback noise - gate is activated. when the playback noise - gate activates, the gain on the active hp and line amplifiers are ramped down to their lowest levels. this is equival ent to asserting the minimum - gain controls hp_l_amp_min_gain_en, hp_r_amp_min_gain_en and line_amp_min_gain_en. the noise - gate threshold level can be specified in 6 db steps from 90 db to 48 db. the noise - gate threshold time ranges from 256 samples to 2048 samples and is set using the control dac_ng_setup_time. when the averaged level of the two channels exceeds the release threshold configured in dac_ng_off_threshold, the gain of the amplifiers is ramped up back to its original value. when the average leve l of the two channels is below the attack threshold configured in dac_ng_on_threshold for longer than the time specified in dac_ng_setup_time, the gain is ramped down to its minimum value. the attack and release rate can be configured via controls dac_ng_r ampdn_rate and dac_ng_rampup_rate. the noise - gate release time is usually much faster than the attack time, to allow a proper playback as soon as a signal is present at the output amplifiers.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 47 of 129 ? 2015 dialog semiconductor 13.25 clock m odes the DA7212 requires a clock for operation of various circuits within the chip. there are four ways in which the main system clock may be generated: pll bypass mode : if digital playback or record is required, the mclk frequency should be set to one of 11.2896/12.288 mhz or 22.5792/24 .576 mhz or 45.1584/49.152 mhz ( note 17 ). the pll_indiv register bit must then be programmed accordingly normal pll mode : alternative frequency clock applied t o mclk pin (in the range of 2 to 50 mhz), where mclk is synchronous with wclk, or master mode is enabled srm pll mode : clock applied to mclk pin (in the range of 2 to 50 mhz) is asynchronous to wclk 32 khz mode : watch crystal frequency (32.768 khz) clock a pplied to mclk table 33 : pll clock modes mode pll bypassed pll enabled pll enabled srm enabled pll enabled 32 khz enabled master yes ( note 17 ) yes ( note 18 ) no yes ( note 19 ) slave yes ( note 20 ) yes ( note 21 ) yes ( note 22 ) no note 17 11.2896 mhz (or multiples) should be used as mclk frequency for 11.025, 22.05, 44.1, 88.2 khz sample rates and 12.288 mhz (or multiples) should be used for 8, 12, 16, 24, 32, 48, 96 khz sample rates note 18 mclk must be between 2 mhz and 50 mhz note 19 mclk must be 32.768 khz note 20 mclk must be exactly 12.288 mhz or 11.2896 mhz or a multiple thereo f and synchronous with bclk and wclk note 21 mclk must be synchronous with bclk and wcl k note 22 bclk must be synchronous with wclk. mclk must be between 2 mhz and 50 mhz with the default register settings, the clock input should be a square wave with cmos logic levels (r eferenced to vdd_io). a clock squarer circuit can be enabled by asserting the pll_mclk_sqr_en register bit. this clock squarer allows a sine wave or other a low amplitude clock (down to 300 mvpp) to be applied to the codec. the input is ac coupled on chi p when using the clock squarer mode. if the mclk input frequency drops below 1 mhz, the pll_mclk_status bit is cleared, and the chip will automatically use its internal reference oscillator as a clock source.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 48 of 129 ? 2015 dialog semiconductor 13.26 pll bypass m ode if an mclk signal at 11.2896/ 12.288 mhz or 22.5792/24.576 mhz or 45.1584/49.152 mhz is available, the pll is not required and should be disabled to save power. pll bypass mode is activated by clearing the pll enable register bit pll_en. in this mode the pll is bypassed and an audio fr equency clock is applied to the mclk pin of the codec. the required clock frequency depends on the sample rate at which the audio dacs and adcs are operating. these clock frequencies are summarized in table 34 for the range of dac and adc sample rates that can be configured using the sr register. table 34 : sample rate control register and corresponding system clock frequency sample rate, fs (khz) sr r egister system clock frequency (mhz) 8 0001 12.288 11.025 0010 11.2896 12 0011 12.288 16 0101 12.288 22.05 0110 11.2896 24 0111 12.288 32 1001 12.288 44.1 1010 11.2896 48 1011 12.288 88.2 1110 11.2896 96 1111 12.288 if digital playback or record is required in bypass mode then the mclk frequency should be set to 11.2896/12.288 mhz, or to 22.5792/24.576 mhz, or to 45.1584/49.152 mhz and pll_indiv should be programmed accordingly. if no valid mclk is detected, the output of the internal reference oscillator is used instead. however in this case only analogue bypass paths may be used.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 49 of 129 ? 2015 dialog semiconductor 13.26.1 normal pll mode (dai m aster) the DA7212 contains a phase locked l oop (pll) that can be used to generate the required 11.2896 mhz or 12.288 mhz internal system clock when a frequency of between 2 and 50 mhz is applied to mclk. this allows sharing of clocks between devices in an application, reducing total system cost. for example, the codec may operate from common 13 mhz or 19.2 mhz sys tem clock frequency. the pll is enabled by asserting pll_en. once the pll is enabled an d has achieved phase lock, pll bypass m ode is disabled, and the output of the pll is used as the system clock. the pll input d ivider register (pll_indiv) is used to redu ce the pll reference frequency to the usable range of 2 to 5 0 mhz as shown in table 35 reduces the pll reference f requency according to the following equation: f ref = f mclk (2^pll_indiv) table 35 : pll input d ivider mclk input frequency (mhz) input divider, (n) pll_indiv r egister (0x27 [3:2]) 2 C 10 2 00 10 C 20 4 01 20 C 40 8 10 40 C 50 16 11 the value of the pll feedback d ivider is used to set the voltage controlled o scillator (vco) frequency to 8 times the required system clock frequency (see table 34 ) . f vco = f ref pll feedback d ivider the value of the pll feedback d ivider is an unsigned number in the range of 0 to 128. it consists of seven integer bits and 13 fractional bits split across three registers: pll_integer holds the seven integer bits pll_frac_top holds the top bits (msb) of the fractional part of the divisor pll_frac_bot holds the bottom bits (lsb) of the fractional part of the divisor
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 50 of 129 ? 2015 dialog semiconductor 13.26.2 example calculation of the feedback d ivider setting: we will use as an example a codec operating wi th fs (sa mple rate) = 48 khz and a reference input c lock frequency of 12.288 mhz. the required output frequency is 98.304 mhz. the reference clock i nput = 12.288 mhz, which falls in the range 10 - 20 mhz so pll_indiv mus t be set to 0b01 (dividing the referen ce input f requency by 2 C see table 35 . t he formula for calculating the feedback d ivider is: feedback d ivider (f) = vco output frequency * input d ivider (pll_indiv) / r eference input c lock feedback d ivider = (98.304 * 4) / 12.28 8 = 32 so pll_fbdiv_integer (holding the seven integer bits) = 0x20 pll_fbdiv_frac_top (holding the top bits (msb) of the fractional part of the divisor) = 0x00 pll_fbdiv_frac_bot (holding the bottom bits (lsb) of the fractional part of the divisor) = 0x0 0 table 36 shows example register settings that will configure the pll when using a 13 mhz, 15 mhz or 19.2 mhz clock. note that any mclk input frequen cy between 2 and 50 mhz is supported. pll_indiv must be used to reduce the pll reference frequency to the usable range of 2 to 10 mhz as shown in table 36 . table 36 : example pll configurations mclk input frequency (mhz) system clock frequency (mhz) pll_ctrl r egister (see note 23 ) pll_frac_top r egister pll_frac_bot r egister pll_integer r egister 13 11.2896 0x84 0x19 0x45 0x1b 13 12.288 0x84 0x07 0xea 0x1e 15 11.2896 0x84 0x02 0xb4 0x18 15 12.288 0x84 0x06 0xdc 0x1a 19.2 11.2896 0x84 0x1a 0x1c 0x12 19.2 12.288 0x84 0x0f 0x5c 0x14 note 23 any mclk input frequency between 2 and 50 mhz is supported. pll_indiv must be used to reduce the pll reference frequency to the usable range of 2 to 5 mhz.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 51 of 129 ? 2015 dialog semiconductor 13.27 srm pll mode (dai s lave) srm mode enables the pll output clock to be synchronized to the incoming wclk signal on the dai. the srm pll mode is enabled by setting the pll as for normal pll mode and asserting register bit pll_srm_en. register bit srm_lock indicates whether or not the srm has achieved synchronis ation with wclk. when using the digital audio interface in slave mode with the srm enabled, removing and re - applying the dai interface word clock wclk may cause the pll lock to be lost. to re - lock the pll it is recommended that you disable the srm (pll_srm_en = 0), reset the pll by re - writing to register pll_integer, and then re - enable the srm (pll_srm_en = 1) after the dai wclk has been reapplied. when switching sample rates between 44.1 khz and 48 khz (or between the multiples of these sample rates), srm must be disabled and then re enabled using register bit pll_srm_en. 13.28 32 khz pll mode (dai m aster) 32 khz mode enables the pll output clock to be synchronized to a 32.768 khz clock signal on the mclk pin. 32 khz pll mode is select ed by enabling the pll and asserting both pll_srm_en and pll_32k_mode. register bit pll_ srm_lock indicates whether or not the srm has achieved synchronis ation with mclk. 13.29 operating with a 2 mhz to 5 mhz mclk w hen using the pll with a 2 mhz - 5 mhz mclk, you m ust follow the procedure below to setup the pll in the correct mode. setup pll and clocking write f0 = 8b write f1 = 03 write f0 = 00 when returning from this mode to a mode with an mclk >5 mhz, you must follow the procedure below. write f0 = 8b write f1 = 01 write f0 = 00 setup pll and clocking 13.30 mixed sample r ates in DA7212 there is only one sample rate register and therefore, by default, this controls the sample rate of both the adc and the dac some applications require the adc and the dac to run at different sample rates. a special mode (24 - 48 mode) is available by asserting 24_48_mode at register address 0x84[0]. asserting this bit sets the adc to run at 24 khz and the dac to run at 48 khz. in this mode all the functionality of the adc and the dac i s available. the dai will continue to run at 48 khz, and every adc sample will be repeated across two wclk frames.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 52 of 129 ? 2015 dialog semiconductor 13.31 i2c control i nterface the DA7212 is completely software - controlled from the host by registers. the DA7212 provides an i2c compliant serial control interface to access these registers. data is shifted into or out of the DA7212 under the control of the host processor, which also provides the serial clock. the 7 - bit i2c slave address is 0x1a so that the 8 - bit address for writing is 0x34 and for reading is 0x35. the i2c clock is supplied by the scl line and the bi - directional i2c data is carried by the sda line. the i2c interface is open - drain supporting multiple devices on a single line. the bus lines have to be pulled high by external pull - up r esistors (1 k? to 20 k? range). the attached devices only drive the bus lines low by connecting them to ground. this means that two devices cannot conflict if they drive the bus simultaneously. in standard/fast mode the highest frequency of the bus is 1 mh z. the exact frequency can be determined by the application and does not have any relation to the DA7212 internal clock signals. DA7212 will follow the host clock speed within the described limitations and does not initiate any clock arbitration or slow do wn. in high - speed mode the maximum frequency of the bus can be increased up to 3.4 mhz. this mode is supported if the scl line is driven with a push - pull stage from the host and if the host enables an external 3 ma pull - up at the sda pin to decrease the ri se time of the data. in this mode the sda line on DA7212 is able to sink up to 12 ma. in all other respects the high speed mode behaves as the standard/fast mode. communication on the i2c bus always takes place between two devices, one acting as the master and the other as the slave. the DA7212 will only operate as a slave. the i2c interface has direct access to the whole register map of the DA7212 . figure 20 : schematic of the i2c control interface bus h o s t p r o c e s s o r c o d e c s d a s c l p e r i p h e r a l d e v i c e s d a s c l s c l s d a v d d _ i o v d d _ i o
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 53 of 129 ? 2015 dialog semiconductor 13.32 details of the i2c c ontrol interface protocol all data is transmitted across the i2c bus in groups of 8 bits. to send a bit the sda line is driven to the intended state while the sda is low (a low on sda indicates a zero bit). once the sda has settled, the scl line is brought high and then low. this pulse on scl clocks the sda bit into the receivers shift register. a two byte serial protocol is used containing one byte for address and one byte for data. data and address transfer is transmitted msb fir st for both read and write operations. all transmission begins with the start condition from the master while the bus is in the idle state (the bus is free). it is initiated by a high to low transition on the sda line while the scl is in the high state (a stop condition is indicated by a low to high transition on the sda line while the scl line is in the high state). figure 21 timing of i2c start and stop c onditions the i2c bus is monitored by DA7212 for a valid slave address whenever the interface is enabled. it responds with an acknowledge immediately when it receives its own slave address. the acknowledge is done by pulling the sda line low during the following clock cycle (white blocks marked with a in figure 22 to figure 25 ). the protocol for a register write from master to slave consists of a s tart condition, a slave address with read/write bit and the 8 - bit register address followed by 8 bits of data terminated by a stop condition (the DA7212 responds to all bytes with acknowledge). this is illustrated in figure 22 . figure 22 : i2c b yte write (sda signal) when the host reads data from a register it first has to write - access DA7212 with the target register address and then read access DA7212 with a repeated start, or alternatively a second start condition. after receiving the data the host sends a not acknowledge (nak) and terminates the transmission with a stop condition: figure 23 : examples of the i2c byte r ead (sda line) s c l s d a slave a d dr w reg a d dr a data a p s = start condition a = acknowledge ( low) p = stop condition w = write (low) master to slave slave to master 7 - bits 1 - bit 8 - bits 8 - bits a s s slavea d dr w a reg ad dr a slavead d r a s = start condition a = acknowledge ( low) sr = repeated start condition a * = no t a cknowledge (na k) p = stop condition w = write (low) r = read (high) master to slave 7 - bits 1 - bit 8 - bits 7 - bits data a * sr r 1 - bit 8 - bits slavead d r a 7 - bits data p s r 1 - bit 8 - bits p a * slave to master s slavea d dr w a reg ad d r p 7 - bits 1 - bit 8 - bits a
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 54 of 129 ? 2015 dialog semiconductor consecutive (page mode) read - out mode (cif_i2c_write_mode (0x1d [0]) = 0) is initiated from the master by sending an acknowledge instead of not acknowledge (nak) after receipt of the data word. the i2c control block then increments the address pointer to the next i2c address and sends the data to the master. this enables an unlimited read of data bytes until the master sends a nak directly after the receipt of data , followed by a subsequent stop condition. if a non - existent i2c address is read out, the DA7212 will return code zero. figure 24 : examples of i2c page r ead (sda line) the slave address after the repeated start condition must be the same as the previous slave address consecutive write - mode (cif_i2c_write_mode (0x1d [0]) = 0) is supported if the m aster sends several data bytes following a slave register address. the i2c control block then increments the add ress pointer to the next i2c address, stores the received data and sends an a cknowledge until the master sends the stop condition. figure 25 : i2c page write (sda l ine) an alternative repeated - write mode t hat uses non - consecutive slave register addresses is available using the cif_i2c_write_mode register. in this repeat mode (cif_i2c_write_mode (0x1d [0] ) = 1), the slave can be configured to support a hosts repeated write operations into several non - consecutive registers. data is stored at the previously received register address. if a new start or stop condition occurs within a message , the bus returns to idle mode. this is illustrated in figure 26 . figure 26 : i2c repeated write (sda l ine) i n page mode (cif_i2c_write_mode = 0), both page mode reads and writes using auto - incremented addresses, and repeat mode reads and writes using non auto - incremented addresses, are supported. in repeat mode (cif_i2c_write_mode = 1) however, only repeat mode reads a nd writes are supported. s slavead d r w a reg ad d r a slavead d r a s = st art condition a = acknowledge (low) sr = repeat start condition a * = no t acknowledge (nak) p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 7 - bits data a sr r 1 - bit 8 - bits s slavead d r w a reg ad d r a slavead d r a 7 - bits 1 - bit 8 - bits 7 - bits data p s r 1 - bit 8 - bits p a a * p data data a a * data 8 - bits 8 - bits 8 - bits s slavead d r w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no t acknowledge (nak) p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits data a 1 - bit 8 - bits a p data . a 8 - bits repeated writes s slavead d r w a reg ad d r a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no t acknowledge (nak) p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits reg ad d r a 1 - bit 8 - bits a p data . a 8 - bits repeated writes
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 55 of 129 ? 2015 dialog semiconductor 13.33 digital audio i nterface (dai) DA7212 provides one digital audio i nterface (dai) to input dac data or to output adc data. it is enabled by asserting dai_en. the dsp provides flexible routing options allowing each interface to be con nected to different signal paths as desired in each application. the dai consists of a four - wire serial interface, with bit clock (bclk), word clock (wclk), data - in (datin) and data - out (datout) pins. both master and slave clock modes are supported by the DA7212 . master mode is enabled setting register dai_clk_en (0x28[7]) = 1. in master mode, the bit clock and word clock signals are outputs from the codec. in slave mode these are inputs to the codec. figure 27 : master m ode (dai_clk_en = 1) figure 28 : slave m ode (dai_clk_en = 0) the internal serialized dai data is 24 bits wide. serial data that is not 24 bits wide is either shortened or zero - filled at input to, or at output from, the dais internal 24 - bit data width. the serial data word length can be configured to be 16, 20, 24 or 32 bits wide using the dai_word_length register bits. four different data formats are supported by the digital audio interface. the data format is determined by the setting of the dai_format register bits. i2s mode left justified mode right justified mode dsp mode time division multiplexing (tdm) is available in any of these modes to support the case where multiple devic es are communicating simultaneously on the same bus. tdm is enabled by ass erting the dai_tdm_mode_en bit. d a 7 2 1 2 c o d e c p r o c e s s o r b c l k w c l k d a t i n d a t o u t d a 7 2 1 2 c o d e c p r o c e s s o r b c l k w c l k d a t i n d a t o u t
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 56 of 129 ? 2015 dialog semiconductor 13.34 i2s m ode in i2s mode (dai_format = 0), the msb of the left channel is valid on the second rising edge of the bit clock after the falling edge of the w ord clock. the msb of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock, and the msb of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word cloc k. figure 29 : i2s m ode 13.35 left j ustifi ed m ode in left - justified mode (dai_format = 1), the msb of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. the msb of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock. figure 30 : left justified m ode 13.36 right j ustifi ed m ode in right - justified mode (dai_format = 2), the lsb of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. the lsb of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. figure 31 : right justified m ode b c l k w c l k m s b r i g h t c h a n n e l l s b m s b l e f t c h a n n e l l s b d a t i n / d a t o u t m s b w c l k 1 = r i g h t c h a n n e l d a t a w c l k 0 = l e f t c h a n n e l d a t a b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t m s b w c l k 1 = l e f t c h a n n e l d a t a w c l k 0 = r i g h t c h a n n e l d a t a b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t l s b w c l k 1 = l e f t c h a n n e l d a t a w c l k 0 = r i g h t c h a n n e l d a t a
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 57 of 129 ? 2015 dialog semiconductor 13.37 dsp m ode in dsp mode (dai_format = 3), the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. each data bit is valid on the falling edge of the bit clock. figure 32 : dsp m ode b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t m s b t h e f a l l i n g e d g e o f w c l k c a n o c c u r a n y w h e r e i n t h i s a r e a t h e f a l l i n g e d g e o f w c l k c a n o c c u r a n y w h e r e i n t h i s a r e a b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t m s b o f f s e t
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 58 of 129 ? 2015 dialog semiconductor 13.38 time division multiplexing (tdm) m ode time division m ultiplexing (tdm) allows multiple devices to communicate on the same bus without conflicting. tdm mode (dai_tdm_mode_en = 1) is a n extension of the dsp and the left j ustified formats (see page 56 ). figure 33 : tdm e xample (slave mode) figure 34 : tdm m ode (left justified mode) a time offset is specified from the normal start of frame condition using register bit dai_offset. since a different offset may be defined for each device on the bus, they may both communicate without collisions. in the left j ustified tdm example illustrated in figure 34 , the left channel data is valid dai_offset clock cycles after the rising edge of the word clock, and the right channel data is valid the same dai_off set number of clock cycles after the falling edge of the word clock. d a 7 2 1 2 c o d e c p r o c e s s o r d a 7 2 1 2 c o d e c b i t c l o c k w o r d c l o c k d a c d a t a i n a d c d a t a o u t b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t m s b w c l k 1 = l e f t c h a n n e l d a t a w c l k 0 = r i g h t c h a n n e l d a t a b c l k w c l k m s b l e f t c h a n n e l l s b m s b r i g h t c h a n n e l l s b d a t i n / d a t o u t m s b w c l k 1 = l e f t c h a n n e l d a t a w c l k 0 = r i g h t c h a n n e l d a t a o f f s e t
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 59 of 129 ? 2015 dialog semiconductor in dsp tdm mode (not illustrated), the left channel data is valid after the same dai_offset clock cycles from the rising edge of the word clock, but the right channel data is valid immedi ately after the left channel data. the serial data pin must be tri - stated whenever the output is not valid. mono mode is supported in the tdm mode by asserting dai_mono_mode_en. if dai_mono_mode_en is asserted, only the data from the digital audio interfac e left channel is transmitted. 13.38.1 configuration of the digital audio i nterface the data format is configured using register dai_format. the offset applied in tdm mode is configured using register dai_offset. the word length is configured using register dai_wo rd_length. the digital audio interface is enabled using register dai_en and the frame length is configured using dai_bclks_per_wclk. when using the digital audio interface in slave mode (dai_clk_en = 0), if the wclk input is not from the same clock source as the mclk input, then the srm pll mode must be enabl ed to maintain synchronization. 13.39 pop - free and click - free start - up using the system c ontrollers DA7212 has two system c ontrollers that provide pop - free and click - free start - up under most conditions. 13.39.1 level 1 system c ontroller (scl1) the level 1 system c ontroller (scl1) is automatically activated whenever a sub - systems enable bit is asserted. scl1 ensures that the desired component parts are sequenced in the correct order to provide click - free and pop - free start - up. the following example using the left dac illustrates scl1 in operation. 1. when the left dac is enabled by assertion of the dac_l_en register bit (register 0x69[7] ) a. scl1 first activates the dac clocks b. scl1 then activates the dsp logic c. next, scl1 activates the analogue dac d. finally, scl1 ramps up the digital gain in this way, scl1 helps ensure that the dac_l start - up is free of pops and clicks. note, if any dependent functions for a sub - systems activation have not been enabled, scl1 will not automa tically enable them. this allows you greater control over the sequencing of the sub - system, but it also means that any sub - system can potentially be brought up in such a way that audible artefacts such as pops and clicks are introduced.
DA7212 ul tra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 60 of 129 ? 2015 dialog semiconductor 13.39.2 level 2 system c o ntroller (scl2) level 2 system c ontroller (scl2) is a higher level controller that provides one - touch activation of standard operating modes. input or output sub - systems can be activated either singly or in combination. all selected sub - systems will start up in the correct order and without pops or clicks when scl2 is activated. first, the desired input sub - systems must be selected by asserting the relevant fields (bits 1 to 7) of the system_modes_input (0x50) register. similarly, the desired output sub - s ystems must be selected by asserting the relevant fields (bits 1 to 7) of the system_modes_output (0x51) register. once the desired sub - systems have been selected, the scl2 controller is activated by writing 1 to the mode_submit register field in either the system_modes_input (0x50) or the system_modes_output (0x51) register. it does not matter which of the two mode_submit fields is asserted. both work in the same way, and each will start up both the input and the output sub - systems. when scl2 is activa ted by asserting mode_submit, all of the register - writes that are required by the selected sub - systems are performed automatically. each sub - system is brought up in the correct order to avoid pops and clicks, and within each sub - system, the component parts are brought up in the correct pop - free and click - free sequence. t he mode_submit field used to start scl2 is self - clearing, and is automatically reset to 0 once scl2 has started . scl1 and scl2 activity can be monitored using the scl1_busy and scl2_busy b its on the system_status (0xe0) register. if the DA7212 device is changed from one playback mode to another, or if it is changed from one record mode to another, the initial mode is closed down first before the second mode is activated. this happens automa tically . 13.40 power supply C standby m ode DA7212 has an ultra - low power standby mode that can be enabled to save power when the device is not in use. standby m ode is controlled using the system_active register. 13.40.1 entering standby m ode standby m ode is activated by writing a 0 to the system_active register bit. this system_active r egister cannot be read when in standby m ode because the act of reading the bit causes it to be asserted, which causes the standby m ode to be exited. when entering s ta ndby m ode, it is important that all audio paths are shut down first because the sh ut down is abrupt and audio arte facts such as pops and click may be heard. no audio functions are possible during standby m ode, as the reference oscillator and the reference voltages are both shut down. 13.40.2 exiting standby m ode standby m ode can be exited by writing a 1 to the system_active register bit. any read or write access to the DA7212 will also cause the system_active bit to be asserted, but note that the first read or write access may fa il because of the time taken to restart the reference oscillator. it is recommended that standby m ode is exited by writing to the system_active register rather than relying on the automatic assertion of the register by a read or write access. read or write accesses to i2c slave addresses other than those used by the DA7212 will not cause standby m ode to be exited .
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 61 of 129 ? 2015 dialog semiconductor 14 register definitions 14.1 register map addr function 7 6 5 4 3 2 1 0 status r egisters 0x02 status1 reserved reserved reser ved reserved reserved reserved reserved reserved 0x03 pll_status reserved reserved reserved reserved pll_bypass_activ e pll_mclk_status pll_srm_lock pll_lock 0x04 aux_l_gain_status reserved reserved aux_l_amp_gain_status 0x05 aux_r_gain_status reserved reserved aux_r_amp_gain_status 0x06 mic_1_gain_status reserved reserved reserved reserved reserved mic_1_amp_gain_status 0x07 mic_2_gain_status reserved reserved reserved reserved reserved mic_2_amp_gain_status 0x08 mixin_l_gain_status res erved reserved reserved reserved mixin_l_amp_gain_status 0x09 mixin_r_gain_status reserved reserved reserved reserved mixin_r_amp_gain_status 0x0a adc_l_gain_status reserved adc_l_digital_gain_status 0x0b adc_r_gain_status reserved adc_r_digital_gain_status 0x0c dac_l_gain_status reserved dac_l_digital_gain_status 0x0d dac_r_gain_status reserved dac_r_digital_gain_status 0x0e hp_l_gain_status reserved reserved hp_l_amp_gain_status 0x0f hp_r_gain_status reserved reserved hp_r_amp_gain_status 0x10 line_gain_status reserved reserved line_amp_gain_status system initialisation r egisters 0x1d cif_ctrl cif_reg_soft_ reset reserved reserved reserved reserved reserved reserved cif_i2c_write_mod e 0x21 dig_routing_dai reserved reserved dai_r_src reserved reserved dai_l_src 0x22 sr reserved reserved reserved reserved sr 0x23 references reserved reserved vmid_fast_discha rge vmid_fast_charg e bias_en reserved reserved reserved 0x24 pll_frac_top reserved reserved reserved pll_fbdiv_frac_top
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 62 of 129 ? 2015 dialog semiconductor addr function 7 6 5 4 3 2 1 0 0x25 pll_frac_bot pll_fbdiv_frac_bot 0x26 pll_integer reserved pll_fbdiv_integer 0x27 pll_ctrl pll_en pll_srm_en pll_32k_mode pll_mclk_sqr_en pll_indiv reserved reserved 0x28 dai_clk_mode dai_clk_en reserved reserved reserved dai_wclk_pol dai_clk_pol dai_bclks_per_wclk 0x29 dai_ctrl dai_en dai_oe dai_tdm_mode_en dai_mono_mode_ en dai_word_length dai_format 0x2a dig_routing_dac dac_r_mono reserved dac_r_src dac_l_mono reserved dac_l_src 0x2b alc_ctrl1 alc_r_en reserved alc_calib_overfl ow alc_auto_calib_e n alc_l_en alc_calib_mode alc_sync_mode alc_offset_en input gain / select filter r egisters 0x 30 aux_l_gain reserved reserved aux_l_amp_gain 0x 31 aux_r_gain reserved reserved aux_r_amp_gain 0x 32 mixin_l_select dmic_l_en reserved reserved mixin_l_sel mic2_sel mic1_sel aux_l_sel 0x 33 mixin_r_select dmic_r_en reserved reserved mixin_l_sel mic1_sel mic2_sel aux_r_sel 0x 34 mixin_l_gain reserved reserved reserved reserved mixin_l_amp_gain 0x 35 mixin_r_gain reserved reserved reserved reserved mixin_r_amp_gain 0x 36 adc_l_gain reserved adc_l_digital_gain 0x 37 adc_r_gain reserved adc_r_digital_gain 0x 38 adc_filters1 adc_hpf_en reserved adc_audio_hpf_corner adc_voice_en adc_voice_hpf_corner 0x 39 mic_1_gain reserved reserved reserved reserved reserved mic_1_amp_gain 0x 3a mic_2_gain reserved reserved reserved reserved reserved mic_2_amp_gain output gain / select filter r egisters 0x 40 dac_filters5 dac_softmute _en dac_softmute _ r ate reserved reserved reserved reserved 0x 41 dac_filters2 dac_eq_band2 dac_eq_band1 0x 42 dac_filters3 dac_eq_band4 dac_eq_band3 0x 43 dac_filters4 dac_eq_en reserved reserved reserved dac_eq_band5 0x 44 dac_filters1 dac_hpf_en reserved dac_audio_hpf_corner dac_voice_en dac_voice_hpf_corner 0x 45 dac_l_gain reserved dac_l_digital_gain
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 63 of 129 ? 2015 dialog semiconductor addr function 7 6 5 4 3 2 1 0 0x 46 dac_r_gain reserved dac_r_digital_gain 0x 47 cp_ctrl cp_en cp_small_switc h_freq_en cp_mchange cp_mod cp_analogue_lvl 0x 48 hp_l_gain reserved reserved hp_l_amp_gain 0x 49 hp_r_gain reserved reserved hp_r_amp_gain 0x 4a line_gain reserved reserved line_amp_gain 0x 4b mixout_l_select reserved mixin_r_inv mixin_l_inv aux_l_inv dac_l mixin_r mixin_l aux_l 0x 4c mixout_r_select reserved mixin_l_inv mixin_r_inv aux_r_inv dac_r mixin_l mixin_r aux_r system controller r egisters (1) 0x 50 system_modes_inpu t adc_r adc_l mixin_r mixin_l mic_2 mic_1 reserved mode_submit 0x 51 system_modes_outp ut dac_r dac_l hp_r hp_l line aux_r aux_l mode_submit control r egisters (2) 0x 60 aux_l_ctrl aux_l_amp_en aux_l_amp_mut e_en aux_l_amp_ramp_ en aux_l_amp_zc_en aux_l_amp_zc_sel reserved reserved 0x 61 aux_r_ctrl aux_r_amp_en aux_r_amp_mut e_en aux_r_amp_ramp_ en aux_r_amp_zc_en aux_r_amp_zc_sel reserved reserved 0x 62 micbias_ctrl micbias2_en reserved micbias2_level micbias1_en reserved micbias1_lvl 0x 63 mic_1_ctrl mic_1_amp_en mic_1_amp_mut e_en reserved reserved mic_1_amp_in_sel reserved reserved 0x 64 mic_2_ctrl mic_2_amp_en mic_2_amp_mut e_en reserved rese rved mic_2_amp_in_sel reserved reserved 0x 65 mixin_l_ctrl mixin_l_amp_en mixin_l_amp_mu te_en mixin_l_amp_ramp _en mixin_l_amp_zc_e n mixin_l_mix_en reserved reserved reserved 0x 66 mixin_r_ctrl mixin_r_amp_e n mixin_r_amp_mu te_en mixin_r_amp_ram p_en mixin_r_amp_zc_e n mixin_r_mix_en reserved reserved reserved 0x 67 adc_l_ctrl adc_l_en adc_l_mute_en adc_l_ramp_en reserved reserved reserved reserved reserved 0x 68 adc_r_ctrl adc_r_en adc_r_mute_en adc_r_ramp_en reserved reserved reserved reserved reserved 0x 69 dac_l_ctrl dac_l_en dac_l_mute_en dac_l_ramp_en reserved reserved reserved reserved reserved
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 64 of 129 ? 2015 dialog semiconductor addr function 7 6 5 4 3 2 1 0 0x 6a dac_r_ctrl dac_r_en dac_r_mute_en dac_r_ramp_en reserved reserved reserved reserved reserved 0x 6b hp_l_ctrl hp_l_amp_en hp_l_amp_mute _en hp_l_amp_ramp_e n hp_l_amp_zc_en hp_l_amp_oe hp_l_amp_min_gai n_en reserved reserved 0x 6c hp_r_ctrl hp_r_amp_en hp_r_amp_mute _en hp_r_amp_ramp_e n hp_r_amp_zc_en hp_r_amp_oe hp_r_amp_min_gai n_en reserved reserved 0x 6d line_ctrl line_amp_en line_amp_mute_ en line_amp_ramp_e n reserved line_amp_oe line_amp_min_gai n_en reserved reserved 0x 6e mixout_l_ctrl mixout_l_amp_ en reserved reserved mixout_l_softmix _en mixout_l_mix_en reserved reserved reserved 0x 6f mixout_r_ctrl mixout_r_amp_ en reserved reserved mixout_r_softmi x_en mixout_r_mix_en reserved reserved reserved mixed sample mode register 0x84 mixed_sample_mode reserved reserved reserved reserved reserved reserved reserved 24_48_mode configuration r egisters 0x90 ldo_ctrl ldo_en reserved ldo_level_select reserved reserved reserved reserved 0x92 gain_ramp_ctrl reserved reserved reserved reserved reserved reserved gain_ramp_rate 0x93 mic_config reserved reserved reserved reserved dmic_clk_rate dmic_samplephas e dmic_data_sel 0x94 pc_count reserved reserved reserved reserved reserved reserved pc_resync_auto pc_freerun 0x95 cp_vol_threshold1 reserved reserved cp_thresh_vdd2 0x96 cp_delay cp_on_off cp_tau_delay cp_fcontrol 0x97 cp_detector reserved reserved reserved reserved reserved reserved cpdet_drop 0x98 dai_offset dai_offset 0x99 dig_ctrl dac_r_inv reserved reserved reserved dac_l_inv reserved reserved reserved 0x9a alc_ctrl2 alc_release alc_attack 0x9b alc_ctrl3 alc_integ_release alc_integ_attack alc_hold 0x9c alc_noise reserved reserved alc_noise 0x9d alc_target_min reserved reserved alc_threshold_min 0x9e alc_threshold_max reserved reserved alc_threshold_max 0x9f alc_gain_limits alc_gain_max alc_atten_max
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 65 of 129 ? 2015 dialog semiconductor addr function 7 6 5 4 3 2 1 0 0xa0 alc_ana_gain_limits reserved alc_ana_gain_max reserved alc_ana_gain_min 0xa1 alc_anticlip_ctrl alc_anticlip_en reserved reserved reserved reserved reserved reserved reserved 0xa2 alc_anticlip_level reserved alc_anticlip_level 0xa3 alc_offset_auto_m_ l reserved reserved reserved reserved reserved reserved reserved reserved 0xa4 alc_offset_auto_u_ l reserved reserved reserved reserved reserved reserved reserved reserved 0xa6 alc_offset_man_m_l reserved reserved reserved reserved reserved reserved reserved reserved 0xa7 alc_offset_man_u_l reserved reserved reserved reserved reserved reserved reserved reserved 0xa8 alc_offset_auto_m_ r reserved reserved reserved reserved reserved reserved reserved reserved 0xa9 alc_offset_auto_u_ r reserved reserved reserved reserved reserved reserved reserved reserved 0xab alc_offset_man_m_ r reserved reserved reserved reserved reserved reserved reserved reserved 0xac alc_offset_man_u_r reserved reserved reserved reserved reserved reserved reserved reserved 0xad alc_cic_op_lvl_ctrl reserved reserved reserved reserved reserved reserved reserved reserved 0xae alc_cic_op_lvl_data reserved reserved reserved reserved reserved reserved reserved reserved 0xaf dac_ng_setup_time reserved reserved reserved reserved dac_ng_rampdn_ rate dac_ng_rampup_r ate dac_ng_setup_time 0xb0 dac_ng_off_thresh old reserved reserved reserved reserved reserved dac_ng_off_threshold 0xb1 dac_ng_on_thresho ld reserved reserved reserved reserved reserved dac_ng_on_threshold 0xb2 dac_ng_ctrl dac_ng_en reserved reserved reser ved reserved reserved reserved reserved tone generation & beep r egisters 0xb4 tone_gen_cfg1 start_stopn reserved reserved dtmf_en dtmf_reg 0xb5 tone_gen_cfg2 gain reserved reserved swg_sel 0xb6 tone_gen_cycles reserved reserved reserved reserved reserved beep_cycles 0xb7 tone_gen_freq1_l freq1_l 0xb8 tone_gen_freq1_u freq1_u
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 66 of 129 ? 2015 dialog semiconductor addr function 7 6 5 4 3 2 1 0 0xb9 tone_gen_freq2_l freq2_l 0xba tone_gen_freq2_u freq2_u 0xbb tone_gen_on_per reserved reserved beep_on_per 0xbc tone_gen_off_per reserved reserved beep_off_per system controller r egisters (2) 0xe0 system_status reserved reserved reserved reserved reserved reserved sc2_busy sc1_busy 0xfd system_active reserved reserved reserved reserved reserved reserved reserved system_active
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 67 of 129 ? 2015 dialog semiconductor 14.2 status registers register address bit type label default description 0x02 status1 7:0 r (reserved) 00000000 register address bit type label default description 0x03 pll_statu s 7:4 r (reserved) 0000 3 r pll_bypass_a ctive 0 indicates whether the pll is in bypass mode 0 = not in bypass mode 1 = bypass mode 2 r pll_mclk_sta tus 0 indicates if the frequency on mclk is greater than 1 mhz 0 = mclk frequency 1 mhz or less 1 = mclk frequency greater than 1 mhz 1 r pll_srm_lock 0 asserted if the srm is locked to the reference signal 0 = srm not locked to reference signal 1 = srm locked to reference signal 0 r pll_lock 0 asserted if the pll is locked to the reference clock 0 = pll not locked to reference clock 1 = pll locked to reference clock register address bit type label default description 0x04 aux_l_gai n_status 7:6 r (reserved) 00 5:0 r aux_l_amp_g ain_status 000000 actual aux_l amplifier gain 000000 to 010001 = - 54 db 010010 = - 52.5 db 010011 = - 51 db continuing in +1.5 db steps to 111110 = 13.5 db 111111 = 15 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 68 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x05 aux_r_gai n_status 7:6 r (reserved) 00 5:0 r aux_r_amp_g ain_status 000000 actual aux_r amplifier gain 000000 to 010001 = - 54 db 010010 = - 52.5 db 010011 = - 51 db continuing in +1.5 db steps to 111110 = 13.5 db 111111 = 15 db register address bit type label default description 0x06 mic_1_gai n_status 7:3 r (reserved) 00000 2:0 r mic_1_amp_ga in_status 001 actual mic_1 amplifier gain 000 = - 6 db 001 = 0 db 010 = 6 db and continuing in +6 db steps to 111 = 36 db register address bit type label default description 0x07 mic_2_gai n_status 7:3 r (reserved) 00000 2:0 r mic_2_amp_ga in_status 001 actual mic_2 amplifier gain 000 = - 6 db 001 = 0 db 010 = 6 db and continuing in +6 db steps to 111 = 36 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 69 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x08 mixin_l_ga in_status 7:4 r (reserved) 0000 3:0 r mixin_l_amp_ gain_status 0000 actual in_l amplifier gain 0000 = - 4.5 db 0001 = - 3 db 0010 = - 1.5 db 0011 = 0 db continuing in +1.5 db steps to 1111 = 18 db register address bit type label default description 0x09 mixin_r_g ain_statu s 7:4 r (reserved) 0000 3:0 r mixin_r_amp_ gain_status 0000 actual in_r amplifier gain 0000 = - 4.5 db 0001 = - 3 db 0010 = - 1.5 db 0011 = 0 db continuing in +1.5 db steps to 1111 = 18 db register address bit type label default description 0x0a adc_l_gai n_status 7 r (reserved) 0 6:0 r adc_l_digital _gain_status 0000000 actual adc_l digital gain 0000000 = - 83.25 db 0000001 = - 82.50 db 0000010 = - 81.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12 db note: 1101111 = 0 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 70 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x0b adc_r_gai n_status 7 r (reserved) 0 6:0 r adc_r_digital _gain_status 0000000 actual adc_r digital gain 0000000 = - 83.25 db 0000001 = - 82.50 db 0000010 = - 81.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12 db note: 1101111 = 0 db register address bit type label default description 0x0c dac_l_gai n_status 7 r (reserved) 0 6:0 r dac_l_digital _gain_status 0000000 actual dac_l digital gain 0000000 to 0000111 = mute 0001000 = - 77.25 db 0001001 = - 76.50 db 0001010 = - 75.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12.00 db note: 1101111 = 0 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 71 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x0d dac_r_gai n_status 7 r (reserved) 0 6:0 r dac_r_digital _gain_status 0000000 actual dac_r digital gain 0000000 to 0000111 = mute 0001000 = - 77.25 db 0001001 = - 76.50 db 0001010 = - 75.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12.00 db note: 1101111 = 0 db register address bit type label default description 0x0e hp_l_gain _status 7:6 r (reserved) 00 5:0 r hp_l_amp_gai n_status 000000 actual hp_l amplifier gain 000000 = - 57 db 000001 = - 56 db 000010 = - 55 db continuing in +1 db steps to 111110 = 5 db 111111 = 6 db note: 111001 = 0 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 72 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x0f hp_r_gain _status 7:6 r (reserved) 00 5:0 r hp_r_amp_gai n_status 000000 actual hp_r amplifier gain 000000 = - 57 db 000001 = - 56 db 000010 = - 55 db continuing in +1 db steps to 111110 = 5 db 111111 = 6 db note: 111001 = 0 db register address bit type label default description 0x10 line_gain_ status 7:6 r (reserved) 00 5:0 r line_amp_gai n_status 000000 actual line amplifier gain 000000 = - 48 db 000001 = - 47 db continuing in +1 db steps to 111110 = 14 db 111111 = 15 db note: 110000 = 0 db 14.3 system initialisation registers register address bit type label default description 0x1d cif_ctrl 7 r/w cif_reg_soft _reset 0 software reset that returns all the registers back to the default. writing to this bit causes all the registers to reset 6:1 r/w (reserved) 000000 0 r/w cif_i2c_write _mode 0 mode of operation for the i2c interface 0 = page mode 1 = repeat mode note: page mode supports both page mode and repeat mode reads and writes. repeat mode only supports repeat mode reads and writes.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 73 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x21 dig_routi ng_dai 7:6 r/w (reserved) 00 5:4 r/w dai_r_src 01 data select for the dai right output stream 00 = adc left 01 = adc right 10 = dai input left data 11 = dai input right data 3:2 r/w (reserved) 00 1:0 r/w dai_l_src 00 data select for the dai left output stream 00 = adc left 01 = adc right 10 = dai input left data 11 = dai input right data register address bit type label default description 0x22 sr 7:4 r/w (reserved) 0000 3:0 r/w sr 1010 sample rate control 0001 = 8 khz 0010 = 11.025 khz 0011 = 12 khz 0100 = reserved 0101 = 16 khz 0110 = 22 khz 0111 = 24 khz 1000 = reserved 1001 = 32 khz 1010 = 44.1 khz ( note 24 ) 1011 = 48 khz 1110 = 88.2 khz 1111 = 96 khz note 24 b1011 (48 khz) is the only valid setting when using 24 - 48 mode (24_48_mode = 1)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 74 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x23 referenc es 7 r/w (reserved) 1 6 r/w (reserved) 0 5 r/w vmid_fast_dis charge 0 vmid fast discharge enable: 0 = low noise slow discharge mode 1 = high noise fast discharge mode 4 r/w vmid_fast_ch arge 0 vmid fast charge enable: 0 = low noise slow charge mode 1 = high noise fast charge mode 3 r/w bias_en 0 master bias enable: 0 = disabled 1 = enabled 2 r/w (reserved) 0 1:0 r/w (reserved) 00 register address bit type label default description 0x24 pll_frac_ top 7:5 r/w (reserved) 000 4:0 r/w pll_fbdiv_fra c_top 00000 pll fractional division value (top bits). the full pll fractional division value is a concatenation of these bits (msb) and pll_fbdiv_frac_bot (lsb) register address bit type label default description 0x25 pll_frac_ bot 7:0 r/w pll_fbdiv_fra c_bot 00000000 pll fractional division value (bottom bits). the full pll fractional division value is a concatenation of pll_fbdiv_frac_top (msb) and these bits (lsb) register address bit type label default description 0x26 pll_integ er 7 r/w (reserved) 0 6:0 r/w pll_fbdiv_int eger 0100000 pll integer division value
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 75 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x27 pll_ctrl 7 r/w pll_en 0 pll enable: 0 = system clock is mclk 1 = system clock is pll output 6 r/w pll_srm_en 0 pll sample rate tracking enable: 0 = srm disabled 1 = srm enabled 5 r/w pll_32k_mode 0 sets the pll into 32 khz mode: 0 = disabled 1 = enabled 4 r/w pll_mclk_sqr _en 0 enables the squarer at the mclk: 0 = disabled 1 = enabled 3:2 r/w pll_indiv 11 sets the input clock range for the pll: 00 = 2 - 10 mhz 01 = 10 - 20 mhz 10 = 20 - 40 mhz 11 = 40 - 80 mhz 1:0 r/w (reserved) 00 register address bit type label default description 0x28 dai_clk_m ode 7 r/w dai_clk_en 0 dai master mode enable: 0 = slave mode (bclk/wclk inputs) 1 = master mode (bclk/wclk outputs) 6:4 r/w (reserved) 000 3 r/w dai_wclk_pol 0 dai word clock polarity: 0 = normal polarity 1 = inverted polarity 2 r/w dai_clk_pol 0 dai bit clock polarity: 0 = normal 1 = inverted 1:0 r/w dai_bclks_pe r_wclk 01 dai master mode bclk number per wclk period: 00 = bclk = 32 01 = bclk = 64 10 = bclk = 128 11 = bclk = 256
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 76 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x29 dai_ctrl 7 r/w dai_en 0 dai enable: 0 = disabled 1 = enabled 6 r/w dai_oe 0 dai output enable: 0 = datout pin is high impedence 1 = datout pin is driven when required 5 r/w dai_tdm_mod e_en 0 dai tdm mode enable: 0 = dai normal mode 1 = dai tdm mode 4 r/w dai_mono_mo de_en 0 dai mono mode enable: 0 = dai stereo mode 1 = dai mono mode dai mono mode can only be enabled when the dsp data format = dsp mode (dai_format = 11) 3:2 r/w dai_word_le ngth 10 dai data word length: 00 = 16 bits per channel 01 = 20 bits per channel 10 = 24 bits per channel 11 = 32 bits per channel 1:0 r/w dai_format 00 dai data format: 00 = i2s mode 01 = left justified mode 10 = right justified mode 11 = dsp mode
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 77 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x2a dig_routi ng_dac 7 r/w dac_r_mono 0 when asserted, the dai right input stream is replaced with a mono mix of left and right 0 = right input stream 1 = mono mix of left and right input streams 6 r/w (reserved) 0 5:4 r/w dac_r_src 11 data select to the dac_r path: 00 = adc left output 01 = adc right output 10 = determined by dac_l_mono (bit [3] of this register) 11 = determined by dac_r_mono (bit [7] of this register) note: the beep generator is omited from the signal path if this is set to 00 or 01 3 r/w dac_l_mono 0 when asserted, the dai left input stream is replaced with a mono mix of left and right 0 = left input stream 1 = mono mix of left and right input streams 2 r/w (reserved) 0 1:0 r/w dac_l_src 10 data select to the dac_l path: 00 = adc left output 01 = adc right output 10 = determined by dac_l_mono (bit [3] of this register) 11 = determined by dac_r_mono (bit [7] of this register) the beep generator is omited from the signal path if this is set to 00 or 01
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 78 of 12 9 ? 2015 dialog semiconductor register address bit type label default description 0x2b alc_ctrl1 7 r/w alc_r_en 0 enables the alc operation on the right adc channel: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5 r alc_calib_ov erflow 0 offset overflow during calibration 0 = no offset overflow 1 = offset overflow 4 r/w alc_auto_cal ib_en 0 automatic calibration enable (self clearing bit) 0 = disabled 1 = enabled 3 r/w alc_l_en 0 enables the alc operation on the left adc channel: 0 = disabled 1 = enabled 2 r/w alc_calib_mo de 0 calibration mode 0 = automatic calibration 1 = manual calibration 1 r/w alc_sync_mo de 0 selects the alc operation mode: 0 = full digital gain solution 1 = mixed digital/analogue gain solution 0 r/w alc_offset_e n 0 enable dc offset cancellation: 0 = disabled 1 = enabled 14.4 input gain/select filter registers register address bit type label default description 0x 30 aux_l_gai n 7:6 r/w (reserved) 00 5:0 r/w aux_l_amp_g ain 110101 gain setting for the aux left amplifier (1.5 db step): 000000 to 010001 = - 54 db 010010 = - 52.5 db 010011 = - 51 db continuing in +1.5 db steps to 111110 = 13.5 db 111111 = 15 db note: 110101 = 0 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 79 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 31 aux_r_gai n 7:6 r/w (reserved) 00 5:0 r/w aux_r_amp_g ain 110101 gain setting for the aux right amplifier (1.5 db step): 000000 to 010001 = - 54 db 010010 = - 52.5 db 010011 = - 51 db continuing in +1.5 db steps to 111110 = 13.5 db 111111 = 15 db note: 110101 = 0 db (default) register address bit type label default description 0x 32 mixin_l_se lect 7 r/w dmic_l_en 0 enable the left dmic input: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5:4 r/w (reserved) 00 3 r/w mixin_r 0 0 = mixin_r not mixed in 1 = mixin_r mixed in 2 r/w mic2_sel 0 0 = mic2 input not mixed in 1 = mic2 input mixed in 1 r/w mic1_sel 0 0 = mic1 input not mixed in 1 = mic1 input mixed in 0 r/w aux_l_sel 0 0 = aux_l input not mixed in 1 = aux_l input mixed in
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 80 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 33 mixin_r_s elect 7 r/w dmic_r_en 0 enable the right dmic input: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5:4 r/w (reserved) 00 3 r/w mixin_l_sel 0 0 = mixin_l input not mixed in 1 = mixin_l input mixed in 2 r/w mic1_sel 0 0 = mic_1 input not mixed in 1 = mic_1 input mixed in 1 r/w mic2_sel 0 0 = mic_2 input not mixed in 1 = mic_2 input mixed in 0 r/w aux_r_sel 0 0 = aux_r input not mixed in 1 = aux_r input mixed in register address bit type label default description 0x 34 mixin_l_ga in 7:4 r/w (reserved) 0000 3:0 r/w mixin_l_amp_ gain 0011 gain setting for the in left amplifier (1.5 db step): 0000 = - 4.5 db 0001 = - 3 db 0010 = - 1.5 db 0011 = 0 db continuing in +1.5 db steps to 1111 = 18 db register address bit type label default description 0x 35 mixin_r_g ain 7:4 r/w (reserved) 0000 3:0 r/w mixin_r_amp_ gain 0011 gain setting for the in right amplifier (1.5 db step): 0000 = - 4.5 db 0001 = - 3 db 0010 = - 1.5 db 0011 = 0 db continuing in +1.5 db steps to 1111 = 18 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 81 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 36 adc_l_gai n 7 r/w (reserved) 0 6:0 r/w adc_l_digital _gain 1101111 adc left digital gain (0.75 db step): 0000000 = - 83.25 db 0000001 = - 82.50 db 0000010 = - 81.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12 db note: 1101111 = 0 db (default) register address bit type label default description 0x 37 adc_r_gai n 7 r/w (reserved) 0 6:0 r/w adc_r_digital _gain 1101111 adc right digital gain (0.75 db step): 0000000 = - 83.25 db 0000001 = - 82.50 db 0000010 = - 81.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12 db note: 1101111 = 0 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 82 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 38 adc_filte rs1 7 r/w adc_hpf_en 1 adc high pass filter enable: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5:4 r/w adc_audio_hp f_corner 00 cut - off frequency at the 3 db for the high pass filter at 48 khz (for other frequencies see table 30 ): 00 = 2 hz 01 = 4 hz 10 = 8 hz 11 = 16 hz 3 r/w adc_voice_en 0 adc voice filter enable: 0 = disabled 1 = enabled 2:0 r/w adc_voice_hp f_corner 000 cut - off frequency at the 3 d b for the voice filter at 8 khz (for other frequencies see table 31 ): 000 = 2.5 hz 001 = 25 hz, 010 = 50 hz 011 = 100 hz 100 = 150 hz 101 = 200 hz 110 = 300 hz 1 11 = 400 hz register address bit type label default description 0x 39 mic_1_gai n 7:3 r/w (reserved) 00000 2:0 r/w mic_1_amp_ga in 001 gain setting for the mic left amplifier (6 db step): 000 = - 6 db 001 = 0 db 010 = 6 db continuing in 6 db steps to 111 = 36 db this setting is ignored if the alc is enabled (alc_r_en or alc_l_en = 1) and the alc is running in syncronised mode (alc_sync_mode = 1)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 83 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 3a mic_2_gai n 7:3 r/w (reserved) 00000 2:0 r/w mic_2_amp_ga in 001 gain setting for the mic right amplifier (6 db step): 000 = - 6 db 001 = 0 db 010 = 6 db continuing in 6 db steps to 111 = 36 db this setting is ignored if the alc is enabled (alc_r_en or alc_l_en = 1) and the alc is running in syncronised mode (alc_sync_mode = 1) 14.5 output gain - filter r egisters register address bit type label default description 0x 40 dac_filte rs5 7 r/w dac_softmut e_en 0 dac soft mute enable on both channels: 0 = disabled 1 = enabled 6:4 r/w dac_softmut e _ r ate 000 softmute gain update rate (samples per 0.1875 db): 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = reserved 3:0 r/w (reserved) 0000
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 84 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 41 dac_filte rs2 7:4 r/w dac_eq_band 2 1000 gain setting for the dac 5 - band eq band 2 (1.5 db steps). 0000 = - 10.5 db 0001 = - 9 db continuing in +1.5 db steps to 1110 = 10.5 db 1111 = 12 db note: 0111 = 0 db note: 1000 = 1.5 db (default) 3:0 r/w dac_eq_band 1 1000 gain setting for the dac 5 - band eq band 1 (1.5 db steps): 0000 = - 10.5 db 0001 = - 9 db continuing in +1.5 db steps to 1110 = 10.5 db 1111 = 12 db note: 0111 = 0 db note: 1000 = 1.5 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 85 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 42 dac_filte rs3 7:4 r/w dac_eq_band 4 1000 gain setting for the dac 5 - band eq band 4 (1.5 db steps). 0000 = - 10.5 db 0001 = - 9 db continuing in +1.5 db steps to 1110 = 10.5 db 1111 = 12 db note: 0111 = 0 db note: 1000 = 1.5 db (default) 3:0 r/w dac_eq_band 3 1000 gain setting for the dac 5 - band eq band 3 (1.5 db steps): 0000 = - 10.5 db 0001 = - 9 db continuing in +1.5 db steps to 1110 = 10.5 db 1111 = 12 db note: 0111 = 0 db note: 1000 = 1.5 db (default) register address bit type label default description 0x 43 dac_filte rs4 7 r/w dac_eq_en 0 dac 5 - band equaliser enable: 0 = disabled 1 = enabled 6:4 r/w (reserved) 000 3:0 r/w dac_eq_band 5 1000 gain setting for the dac 5 - band eq band 5 (1.5 db steps): 0000 = - 10.5 db 0001 = - 9 db continuing in +1.5 db steps to 1110 = 10.5 db 1111 = 12 db note: 0111 = 0 db note: 1000 = 1.5 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 86 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 44 dac_filte rs1 7 r/w dac_hpf_en 1 dac high pass filter enable: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5:4 r/w dac_audio_hp f_corner 00 cut - off frequency at the 3 db for the high pass filter at 48 khz (for other frequencies see table 30 ): 00 = 2 hz 01 = 4 hz 10 = 8 hz 11 = 16 hz 3 r/w dac_voice_en 0 dac voice filter enable: 0 = disabled 1 = enabled t his dac voice filter control overrides the 5 - band eq setting in dac_eq_en 2:0 r/w dac_voice_hp f_corner 000 cut - off frequency at the 3 d b for the voice filter at 8 khz (for other frequencies see table 31 ): 000 = 2.5 hz 001 = 25 hz 010 = 50 hz 011 = 100 hz 100 = 150 hz 101 = 200 hz 110 = 300 hz 111 = 400 hz register address bit type label default description 0x 45 dac_l_gai n 7 r/w (reserved) 0 6:0 r/w dac_l_digital _gain 1101111 dac left digital gain (0.75 db step): 0000000 to 0000111 = mute 0001000 = - 77.25 db 0001001 = - 76.50 db 0001010 = - 75.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12.00 db note: 1101111 = 0 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 87 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 46 dac_r_gai n 7 r/w (reserved) 0 6:0 r/w dac_r_digital _gain 1101111 dac right digital gain (0.75 db step): 0000000 to 0000111 = mute 0001000 = - 77.25 db 0001001 = - 76.50 db 0001010 = - 75.75 db continuing in +0.75 db steps to 1111110 = 11.25 db 1111111 = 12.00 db note: 1101111 = 0 db (default) register address bit type label default description 0x 47 cp_ctrl 7 r/w cp_en 0 charge pump enable: 0 = disabled 1 = enabled 6 r/w cp_small_swi tch_freq_en 1 charge pump low - load low - power mode enable: 0 = disabled 1 = enabled 5:4 r/w cp_mchange 10 charge pump tracking mode select: 00 = voltage level is controlled by cp_mod 01 = voltage level is controlled by the output pga gain setting 10 = voltage level is controlled by the dac signal level 11 = voltage level is controlled by the output signal magnitude 3:2 r/w cp_mod 00 charge pump manual mode level control: 00 = standby 01 = reserved 10 = cpvdd/2 11 = cpvdd/1 1:0 r/w cp_analogue _lvl 01 charge pump analogue feedback control mode: 00 = no feedback 01 = low voltage indicator boosts charge pump 10 = low voltage indicator restarts charge pump cycle 11 = reserved
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 88 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 48 hp_l_gain 7:6 r/w (reserved) 00 5:0 r/w hp_l_amp_gai n 111001 headphone left amplifier gain (1 db step): 000000 = - 57 db 000001 = - 56 db 000010 = - 55 db continuing in +1 db steps to 111110 = 5 db 111111 = 6 db note: 111001 = 0 db (default) register address bit type label default description 0x 49 hp_r_gain 7:6 r/w (reserved) 00 5:0 r/w hp_r_amp_gai n 111001 headphone right amplifier gain (1 db step): 000000 = - 57 db 000001 = - 56 db 000010 = - 55 db continuing in +1 db steps to 111110 = 5 db 111111 = 6 db note: 111001 = 0 db (default) register address bit type label default description 0x 4a line_gain 7:6 r/w (reserved) 00 5:0 r/w line_amp_gai n 110000 line amplifier gain (1 db step) 000000 = - 48 db 000001 = - 47 db continuing in +1 db steps to 111110 = 14 db 111111 = 15 db note: 110000 = 0 db (default)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 89 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 4b mixout_l_ select 7 r/w (reserved) 0 6 r/w mixin_r_inv 0 mixin r inverted control 0 = inverted mixin r not selected 1 = inverted mixin r selected 5 r/w mixin_l_inv 0 mixin l inverted control 0 = inverted mixin l not selected 1 = inverted mixin l selected 4 r/w aux_l_inv 0 aux l inverted control 0 = inverted aux_l not selected 1 = inverted aux_lselected 3 r/w dac_l 0 dac l control 0 = dac_l not selected 1 = dac_l selected 2 r/w mixin_r 0 mixin r control 0 = mixin_r not selected 1 = mixin_r selected 1 r/w mixin_l 0 mixin l control 0 = mixin_l not selected 1 = mixin_lselected 0 r/w aux_l 0 aux_l control 0 = aux_l not selected 1 = aux_l selected
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 90 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 4c mixout_r_ select 7 r/w (reserved) 0 6 r/w mixin_l_inv 0 mixin l inverted control 0 = inverted mixin l not selected 1 = inverted mixin l selected 5 r/w mixin_r_inv 0 mixin r inverted control 0 = inverted mixin r not selected 1 = inverted mixin r selected 4 r/w aux_r_inv 0 aux r inverted control 0 = inverted aux_r not selected 1 = inverted aux_r selected 3 r/w dac_r 0 dac r control 0 = dac_r not selected 1 = dac_r selected 2 r/w mixin_l 0 mixin l control 0 = mixin_l not selected 1 = mixin_l selected 1 r/w mixin_r 0 mixin r control 0 = mixin_r not selected 1 = mixin_r selected 0 r/w aux_r 0 aux_r control 0 = aux_r not selected 1 = aux_r selected
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 91 of 129 ? 2015 dialog semiconductor 14.6 system c ontroll er r egisters register address bit type label default description 0x 50 system_m odes_inpu t 7 r/w adc_r 0 preconfigured system mode - adc_r control 0 = adc_r not used 1 = use adc r 6 r/w adc_l 0 preconfigured system mode - adc_l control 0 = adc_l not used 1 = use adc l 5 r/w mixin_r 0 preconfigured system mode C in_r control 0 = in r amplifier not used 1 = use in_r amplifer 4 r/w mixin_l 0 preconfigured system mode C in_l control 0 = in l amplifier not used 1 = use in_l amplifer 3 r/w mic_2 0 preconfigured system mode C mic_2 control 0 = mic 2 amplifier not used 1 = use mic 2 amplifier 2 r/w mic_1 0 preconfigured system mode C mic_1 control 0 = mic 1 amplifier not used 1 = use mic 1 amplifier 1 r/w (reserved) 0 0 r/w mode_submit 0 system controller 2 activation control 0 = adc_mode and dac_mode inactive 1 = adc_mode and dac_mode active t his register bit is a duplicate of mode_submit (reg 0x51[0]). either register can be used to activate system controller 2. this bit is self - clearing.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 92 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 51 system_m odes_out put 7:3 r/w dac_r 0 preconfigured system mode C dac_r control 0 = dac_r not used 1 = use dac r 6 r/w dac_l 0 preconfigured system mode C dac_l control 0 = dac_l not used 1 = use dac l 5 r/w hp_r 0 preconfigured system mode C hp_r control 0 = hp_r not used 1 = use hp_r amplifier 4 r/w hp_l 0 preconfigured system mode C hp_l control 0 = hp_l not used 1 = use hp_l amplifier 3 r/w line 0 preconfigured system mode C line control 0 = line not used 1 = use line amplifier 2 r/w aux_r 0 preconfigured system mode C aux_r control 0 = aux_r amplifer not used 1 = use aux_r amplifier 1 r/w aux_l 0 preconfigured system mode C aux_l control 0 = aux_l amplifier not used 1 = use aux_l amplifier 0 r/w mode_submit 0 system controller 2 activation control 0 = adc_mode and dac_mode inactive 1 = adc_mode and dac_mode active t his register bit is a duplicate of mode_submit (reg 0x51[0]). either register can be used to activate system controller 2. this bit is self - cleari ng.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 93 of 129 ? 2015 dialog semiconductor 14.7 control r egisters register address bit type label default description 0x 60 aux_l_ctr l 7 r/w aux_l_amp_en 0 aux_l amplifier enable: 0 = disabled 1 = enabled 6 r/w aux_l_amp_m ute_en 1 aux_l amplifier mute enable: 0 = disabled 1 = enabled 5 r/w aux_l_amp_ra mp_en 0 aux_l amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w aux_l_amp_zc _en 0 aux_l amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3:2 r/w aux_l_amp_zc _sel 01 selects where the zero cross detection on the aux_l input is measured: 00 = input of aux_l amplifier 01 = input of aux_l amplifier if gain ? 4.5 db otherwise on the output 10 = neither (no zero cross possible) 11 = output of aux_l amplifier 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 94 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 61 aux_r_ct rl 7 r/w aux_r_amp_e n 0 aux_r amplifier enable: 0 = disabled 1 = enabled 6 r/w aux_r_amp_m ute_en 1 aux_r amplifier mute enable: 0 = disabled 1 = enabled 5 r/w aux_r_amp_r amp_en 0 aux_r amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w aux_r_amp_z c_en 0 aux_r amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3:2 r/w aux_r_amp_z c_sel 01 selects where the zero cross detection on the aux_r input is measured: 00 = input of aux_r amplifier 01 = input of aux_r amplifier if gain ? 4.5 db otherwise on the output 10 = neither (no zero cross possible) 11 = output of aux_r ampli fier 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 95 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 62 micbias_c trl 7 r/w micbias2_en 0 microphone 2 bias enable: 0 = disable 1 = enable 6 r/w (reserved) 0 5:4 r/w micbias2_leve l 01 microphone 2 bias level 00 = 1.6 v 01 = 2.2 v 10 = 2.5 v 11 = 3.0 v 3 r/w micbias1_en 0 microphone 1 bias enable: 0 = disable 1 = enable 2 r/w (reserved) 0 1:0 r/w micbias1_leve l 01 microphone 1 bias level 00 = 1.6 v 01 = 2.2 v 10 = 2.5 v 11 = 3.0 v register address bit type label default description 0x 63 mic_1_ctr l 7 r/w mic_1_amp_en 0 mic_1 amplifier enable: 0 = disabled 1 = enabled 6 r/w mic_1_amp_mu te_en 1 mic_1 amplifier mute enable: 0 = amplifier unmuted 1 = amplifier muted 5 r/w (reserved) 0 4 r/w (reserved) 0 3:2 r/w mic_1_amp_in_ sel 00 mic_1 input source select: 00 = differential 01 = mic_1_p single - ended 10 = mic_1_n single - ended 11 = reserved 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 96 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 64 mic_2_ctr l 7 r/w mic_2_amp_en 0 mic_2 amplifier enable: 0 = disabled 1 = enabled 6 r/w mic_2_amp_mu te_en 1 mic_2 amplifier mute enable: 0 = amplifier unmuted 1 = amplifier muted 5 r/w (reserved) 0 4 r/w (reserved) 0 3:2 r/w mic_2_amp_in_ sel 00 mic_2 input source select: 00 = differential 01 = mic_2_p single - ended 10 = mic_2_n single - ended 11 = reserved 1:0 r/w (reserved) 00 register address bit type label default description 0x 65 mixin_l_ct rl 7 r/w mixin_l_amp_e n 0 mixin_l amplifier enable: 0 = disabled 1 = enabled 6 r/w mixin_l_amp_ mute_en 1 mixin_l amplifier mute enable: 0 = disabled 1 = enabled 5 r/w mixin_l_amp_ ramp_en 0 mixin_l amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w mixin_l_amp_z c_en 0 mixin_l amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3 r/w mixin_l_mix_e n 0 mixin_l mixer enable. when disabled all inputs are deselected: 0 = mixer disabled 1 = mixer enabled 2 r/w (reserved) 0 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 97 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 66 mixin_r_c trl 7 r/w mixin_r_amp_ en 0 mixin_r amplifier enable: 0 = disabled 1 = enabled 6 r/w mixin_r_amp_ mute_en 1 mixin_r amplifier mute enable: 0 = disabled 1 = enabled 5 r/w mixin_r_amp_ ramp_en 0 mixin_r amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w mixin_r_amp_ zc_en 0 mixin_r amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3 r/w mixin_r_mix_e n 0 mixin_r mixer enable. when disabled all inputs are deselected: 0 = mixer disabled 1 = mixer enabled 2 r/w (reserved) 0 1:0 r/w (reserved) 00 register address bit type label default description 0x 67 adc_l_ctr l 7 r/w adc_l_en 0 adc_l enable: 0 = disabled 1 = enabled 6 r/w adc_l_mute_e n 1 adc_l mute enable: 0 = disabled 1 = enabled 5 r/w adc_l_ramp_ en 0 adc_l digital gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4:2 r/w (reserved) 000 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 98 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 68 adc_r_ct rl 7 r/w adc_r_en 0 adc_r enable: 0 = disabled 1 = enabled 6 r/w adc_r_mute_ en 1 adc_r mute enable: 0 = disabled 1 = enabled 5 r/w adc_r_ramp_ en 0 adc_r digital gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4:2 r/w (reserved) 000 1:0 r/w (reserved) 00 register address bit type label default description 0x 69 dac_l_ctr l 7 r/w dac_l_en 0 dac_l enable: 0 = disabled 1 = enabled 6 r/w dac_l_mute_e n 1 dac_l mute enable: 0 = disabled 1 = enabled 5 r/w dac_l_ramp_ en 0 dac_l digital gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w (reserved) 0 3 r/w (reserved) 1 2:0 r/w (reserved) 000
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 99 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 6a dac_r_ct rl 7 r/w dac_r_en 0 dac_r enable: 0 = disabled 1 = enabled 6 r/w dac_r_mute_ en 1 dac_r mute enable: 0 = disabled 1 = enabled 5 r/w dac_r_ramp_ en 0 dac_r digital gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w (reserved) 0 3:0 r/w (reserved) 000 register address bit type label default description 0x 6b hp_l_ctrl 7 r/w hp_l_amp_en 0 hp_l amplifier enable: 0 = disabled 1 = enabled 6 r/w hp_l_amp_mu te_en 1 hp_l amplifier mute enable: 0 = disabled 1 = enabled 5 r/w hp_l_amp_ra mp_en 0 hp_l amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w hp_l_amp_zc_ en 0 hp_l amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3 r/w hp_l_amp_oe 0 hp_l amplfier output enable: 0 = output is high impedence 1 = output is driven 2 r/w hp_l_amp_min _gain_en 0 hp_l amplifiers gain held at the minimum value: 0 = normal gain operation 1 = minimum gain 1:0 r/w (reserved) 01
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 100 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 6c hp_r_ctrl 7 r/w hp_r_amp_en 0 hp_r amplifier enable: 0 = disabled 1 = enabled 6 r/w hp_r_amp_mu te_en 1 hp_r amplifier mute enable: 0 = disabled 1 = enabled 5 r/w hp_r_amp_ra mp_en 0 hp_r amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w hp_r_amp_zc_ en 0 hp_r amplifier zero cross gain update mode enable: 0 = disabled 1 = enabled 3 r/w hp_r_amp_oe 0 hp_r amplfier output enable: 0 = output is high impedence 1 = output is driven 2 r/w hp_r_amp_min _gain_en 0 hp_r amplifiers gain held at the minimum value: 0 = normal gain operation 1 = minimum gain 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 101 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 6d line_ctrl 7 r/w line_amp_en 0 line amplifier enable: 0 = disabled 1 = enabled 6 r/w line_amp_mut e_en 1 line amplifier mute enable: 0 = disabled 1 = enabled 5 r/w line_amp_ram p_en 0 line amplifier gain ramping enable (overrides zero crossing): 0 = disabled 1 = enabled 4 r/w (reserved) 0 3 r/w line_amp_oe 0 line amplfier output enable: 0 = output is high impedence 1 = output is driven 2 r/w line_amp_min _gain_en 0 line amplifiers gain held at the minimum value: 0 = normal gain operation 1 = minimum gain 1:0 r/w (reserved) 00 register address bit type label default description 0x 6e mixout_l_ ctrl 7 r/w mixout_l_amp _en 0 mixout_l mixer amp enable: 0 = disabled 1 = enabled 6 r/w (reserved) 0 5 r/w (reserved) 0 4 r/w mixout_l_sof tmix_en 1 mixout l soft mix enable. when enabled, the gain of any signal that is added to the mixer is ramped up or down at a rate determined by the gain_ramp_rate (0x92[1:0]) setting 0 = disabled 1 = enabled 3 r/w mixout_l_mix _en 0 mixout l mixer enable: 0 = disabled 1 = enabled 2 r/w (reserved) 0 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 102 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x 6f mixout_r_ ctrl 7 r/w mixout_r_am p_en 0 mixout_r mixer amp enable: 0 = disabled 1 = enabled 6:5 r/w (reserved) 00 4 r/w mixout_r_sof tmix_en 1 mixout r soft mix enable. when enabled, the gain of any signal that is added to the mixer is ramped up or down at a rate determined by the gain_ramp_rate (0x92[1:0]) setting 0 = disabled 1 = enabled 3 r/w mixout_r_mix _en 0 mixout r mixer enable: 0 = disabled 1 = enabled 2:0 r/w (reserved) 000 14.8 mixed sample mode r egisters register address bit type label default description 0x84 mixed_sa mple_mod e 7:1 r / w (reserved) 0000000 0 r / w 24_48_mode 0 enables the 24_48_mode of operation. when this bit is asserted, 24_48_mode is activated. the adc path runs at 24 khz and the rest of the system, including the dac path, at 48 khz. note: in 24_48_mode, the system sample rate, which is controlled by bit sr at register address 0x22[3:0], must be set to 1010, or 48 khz. this will make the i2s also run at 48 khz and so the adc o utput , running at 24 khz, will be double sampled. 0 = both adc and dac paths run at a speed determined by the setting of sr at 0x22[3:0] 1 = the adc path runs at 24 khz, and the dac path at 48 khz
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 10 3 of 129 ? 2015 dialog semiconductor 14.9 confi guration r egisters register address bit type label defau lt description 0x90 ldo_ctrl 7 r/w ldo_en 0 audio sub - system digital ldo control. the master bias must be enabled for the ldo to operate. 0 = ldo bypassed 1 = ldo active after powering up from off or from powerdown mode, you must wait for a minimum of 40 ms after the first i2c access before enabling the ldo. failure to wait 40 ms can cause the chip to reset. all other i2c accesses are unaffected. 6 r/w (reserved) 0 5:4 r/w ldo_level_select 00 audio sub - system digital ldo level select: 0 = 1.05 v 1 = 1.10 v 2 = 1.20 v 3 = 1.40 v 3:0 r/w (reserved) 0 register address bit type label default description 0x92 gain_ramp_ ctrl 7:2 r/w (reserved) 000000 1:0 r/w gain_ramp_rate 00 speed of the gain - ramping when activated. 00 = nominal rate / 8 (ramps from zero to maximum in about 1/128 second) 01 = nominal rate / 16 (fastest ramp rate. ramps from zero to maximum in about 1/256 second) 10 = nominal rate * 16 (approximately 1 second fade - in from zero to maximum) 11 = nominal rate * 32 (slowest ramp rate, with approximately 2 second fade - in from zero to maximum) the nominal rate is targeted to be approx 1.28 ms per db for the aux, hp and line, and 0.64 ms per 0.75 db for the adc, dac and mixout
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 104 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x93 mic_confi g 7 r/w (reserved) 0 6 r/w (reserved) 0 5:4 r/w (reserved) 00 3 r/w (reserved) 0 2 r/w dmic_clk_rat e 0 clock rate for the digital microphone is: 0 = 3 mhz 1 = 1.5 mhz 1 r/w dmic_samplep hase 0 phase of the digital microphone: 0 = sample on dmicclk edges 1 = sample between dmicclk edges 0 r/w dmic_data_se l 0 dmic channel select 0 = rising l, falling r 1 = falling l, rising r register address bit type label default description 0x94 pc_count 7:2 r/w (reserved) 000000 1 r/w pc_resync_a uto 1 pc resync mode. if the dai clock drifts away from the system clock, this determines whether the system attempts to resynchronise the clocks (=1) or whether it skips a sample/samples twice (=0). 0 = freerun - double sample if the dai clock is fast, or skip a sample if the dai clock is slow 1 = autoresync upon detection of dai drift with respect to the system clock resynchronising (pc_resync_auto = 1) can reduce the art e facts caused by jitter on either mclk or bclk 0 r/w pc_freerun 0 enables the filter operation when dai is not enabled or no dai clocks are available (adc to dac processing path): 0 = adc and dac filters synchronis ed to the dai 1 = filters free running this should be set to 1 if the adc is feeding the dac directly and no dai clocks are present
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 105 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x95 cp_vol_th reshold1 7:6 r/w (reserved) 00 5:0 r/w cp_thresh_v dd2 100000 threshold at and below which the charge pump can use the cpvdd/2 rail. full details are given in section 13.15 this setting i s only effective when cp_mchange = 10 or cp_mchange = 11. it is ignored for cp_mchange settings of 00 and 01 register address bit type label default description 0x96 cp_delay 7:6 r/w cp_on_off 10 charge pump limiter enable: 00 = limiter on 01 = limiter off 10 = limiter automatically enabled when required 11 = reserved 5:3 r/w cp_tau_delay 010 charge pump voltage decay rate control measured (all values are rounded): 000 = 0 ms 001 = 2 ms 010 = 4 ms 011 = 16 ms 100 = 64 ms 101 = 128 ms 110 = 256 ms 111 = 512 ms 2:0 r/w cp_fcontrol 101 charge pump nominal clock rate. lower rates provide lower power but also drive a lower load. if set to 101 (the default), there is no fixed clock frequency. whenever the hp_pos or hp_neg voltage is low, the clock runs at 1 mhz and stops as soon as the required voltage is reached. 000 = 1 mhz 001 = 500 khz 010 = 250 khz 011 = 125 khz 100 = 63 khz 101 = 0 khz or 1 mhz, depending on demand (analogue mode only) 110 and 111 = reserved
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 106 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x97 cp_detec tor 7:2 r/w (reserved) 000000 1:0 r/w cpdet_drop 00 charge pump maximum voltage droop: 00 = 25 mv 01 = 50 mv 10 = 75 mv 11 = 100 mv register address bit type label default description 0x98 dai_offse t 7:0 r/w dai_offset 0000000 0 dai data offset with respect to wclk. if set to 0, no offset will be inserted relative to the normal formatting. the dai data offset is measured in bclk cycles. register address bit type label default description 0x99 dig_ctrl 7 r/w dac_r_inv 0 0 = dai right input stream is not inverted 1 = dai right input stream is inverted 6:4 r/w (reserved) 000 3 r/w dac_l_inv 0 0 = dai left input stream is not inverted 1 = dai left input stream is inverted 2:0 r/w (reserved) 000
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 107 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x9a alc_ctrl2 7:4 r/w alc_release 0000 sets the alc release rate. this is the speed at which the alc can increase the gain by 1 db. 0000 = 29/fs (0.6 ms/db @48 khz) 0001 = 57/fs (1.2 ms/db @48 khz) 0010 = 115/fs (2.4 ms/db @48 khz) 0011 = 229/fs (4.8 ms/db @48 khz) 0100 = 459/fs (9.6 ms/db @48 khz) 0101 = 917/fs (19.1 ms/db @48 khz) 0110 = 1834/fs (38.2 ms/db @48 khz) 0111 = 3669/fs (76.4 ms/db @48 khz) 1000 = 7338/fs (153 ms/db @48 khz) 1001 = 14676/fs (306 ms/db @48 khz) 1010 to 11111 = 29347/fs (611 ms/db @48 khz) 3:0 r/w alc_attack 0000 sets the alc attack rate, which is the speed at which the alc can decrease the gain by 1 db. 0000 = 7.3/fs (0.15 ms/db @48 khz) 0011 = 15/fs (0.31 ms/db @48 khz) 0010 = 29/fs (0.61 ms/db @48 khz) 0011 = 59/fs (1.2 ms/db @48 khz) 0100 = 117/fs (2.4 ms/db @48 khz) 0101 = 235/fs (4.9 ms/db @48 khz) 0110 = 469/fs (9.8 ms/db @48 khz) 0111 = 938/fs (20 ms/db @48 khz) 1000 = 1876/fs (39 ms/db @48 khz) 1001 = 3753/fs (78 ms/db @48 khz) 1010 = 7506/fs (156 ms/db @48 khz) 1011 = 15012/fs (312 ms/db @48 khz) 1100 to 1111 = 30024/fs (625 ms/db @48 khz)
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 108 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x9b alc_ctrl3 7:6 r/w alc_integ_re lease 00 sets the rate at which the input signal envelope is tracked as the signal gets smaller 00 = 1/4 01 = 1/16 10 = 1/256 11 = reserved (do not use) 5:4 r/w alc_integ_at tack 00 sets the rate at which the input signal envelope is tracked as the signal gets larger: 00 = 1/4 01 = 1/16 10 = 1/256 11 = reserved (do not use) 3:0 r/w alc_hold 0000 sets the alc hold time, which is the the length of time that the alc waits before releasing 0000 = 62/fs (1.3 ms @48 khz) 0001 = 124/fs (2.6 ms @48 khz) 0010 = 248/fs (5.2 ms @48 khz) 0011 = 496/fs (10.3 ms @48 khz) 0100 = 992/fs (20.7 ms @48 khz) 0101 = 1984/fs (41.3 ms @48 khz) 0110 = 3968/fs (82.7 ms @48 khz) 0111 = 7936/fs (165 ms @48 khz) 1000 = 15872/fs (331 ms @48 khz) 1001 = 31744/fs (661 ms @48 khz) 1010 = 63488/fs (1.3 s @48 khz) 1011 = 126976/fs (2.6 s @48 khz) 1100 = 253952/fs (5.3 s @48 khz) 1101 = 507904/fs (10.6 s @48 khz) 1110 = 1015808/fs (21 s @48 khz) 1111 = 2031616/fs (42 s @48 khz) register address bit type label default description 0x9c alc_noise 7:6 r/w (reserved) 00 5:0 r/w alc_noise 111111 sets the threshold below which input signals will not cause the alc to change gain: 000000 = 0 dbfs 000001 = - 1.5 dbfs continuing in - 1.5 dbfs steps to 111111 = - 94.5 dbfs
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 109 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x9d alc_targ et_min 7:6 r/w (reserved) 00 5:0 r/w alc_thresho ld_min 111111 sets the minimum amplitude of the alc output signal before the alc increases the gain. if the maximum allowable gain level is reached then the alc will not increase the gain even if this threshold is breached: 000000 = 0 dbfs 000001 = - 1.5 dbfs continuing in - 1.5 dbfs steps to 111111 = - 94.5 dbfs register address bit type label default description 0x9e alc_targ et _max 7:6 r/w (reserved) 00 5:0 r/w alc_thresho ld_max 000000 sets the maximum amplitude of the alc output signal before the alc decreases the gain. if the maximum attenution level allowed is reached then the alc will not reduce the gain even if this threshold is exceeded: 000000 = 0 dbfs 000001 = - 1.5 dbfs continuing in - 1.5 db steps to 111111 = - 94.5 dbfs
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 110 of 129 ? 2015 dialog semiconductor register address bit type label default description 0x9f alc_gain_ limits 7:4 r/w alc_gain_max 1111 sets the maximum amount of gain that can be applied to the input signal by the alc when the input signal amplitude is smaller than alc_threshold_min: 0000 = 0 db 0001 = 6 db continuing in +6 db steps to 1111 = 90 db 3:0 r/w alc_atten_ma x 1111 sets the maximum amount of attenuation that can be applied to the input signal by the alc when the input signal amplitude is larger than alc_threshold_max: 0000 = 0 db 0001 = 6 db continuing in +6 db steps to 1111 = 90 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 111 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xa0 alc_ana_g ain_limits 7 r/w (reserved) 0 6:4 r/w alc_ana_gain _max 111 sets the maximum amount of analogue gain that can be applied to the input signal by the alc when the input signal amplitude is smaller than alc_threshold_min: 000 = reserved 001 = 0 db 010 = 6 db continuing in +6 db steps to 111 = 36 db 3 r/w (reserved) 0 2:0 r/w alc_ana_gain _min 001 sets the minimum amount of analogue gain that can be applied to the input signal by the alc when the input signal amplitude is larger than alc_threshold_max: 000 = reserved 001 = 0 db 010 = 6 db continuing in +6 db steps to 111 = 36 db register address bit type label default description 0xa1 alc_antic lip_ctrl 7 r/w alc_anticlip_ en 0 enables the alc signal clip prevention mechanism: 0 = disabled 1 = enabled 6:2 r/w (reserved) 00000 1:0 r/w (reserved) 00
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 112 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xa2 alc_antic lip_level 7 r/w (reserved) 0 6:0 r/w alc_anticlip_ level 0000000 sets the threshold above which the alc enters anti - clip operation. the formula for determining the anti - clip level is: (alc_anticlip_level+1)*full scale/128 0000000 = 0.0078*full scale 0000001 = 0.015*full scale continuing in 0.0078 steps to 1111111 = 1.0000*full scale register address bit type label default description 0xaf dac_ng_s etup_time 7:4 r/w (reserved) 0000 3 r/w dac_ng_ramp dn_rate 0 attack rate at which the gain of the output amplifier (hp or line) is reduced: 0 = 0.64 ms/db 1 = 20.48 ms/db 2 r/w dac_ng_ramp up_rate 0 release rate at which the gain of the ouput amplifier (hp or line) is increased: 0 = 0.02 ms/db 1 = 0.16 ms/db 1:0 r/w dac_ng_setu p_time 00 time for which the largest signal through the dacs must be below dac_ng_on_threshold for the noise - gate to mute the data: 00 = 256 samples 01 = 512 samples 10 = 1024 samples 11 = 2048 samples register address bit type label default description 0xb0 dac_ng_o ff_thresh old 7:3 r/w (reserved) 00000 2:0 r/w dac_ng_off_ threshold 000 threshold above which the noise - gate will be deactivated: 000 = - 90 db 001 = - 84 db 111 = - 48 db
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 113 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xb1 dac_ng_o n_thresh old 7:3 r/w (reserved) 00000 2:0 r/w dac_ng_on_t hreshold 000 threshold below which the noise - gate starts to activate: 000 = - 90 db 001 = - 84 db 111 = - 48 db register address bit type label default description 0xb2 dac_ng_c trl 7 r/w dac_ng_en 0 dac noise - gate enable: 0 = disabled 1 = enabled 6:0 r/w (reserved) 0000000 register address bit type label default description 0xb4 tone_gen _cfg1 7 r/w start_stopn 0 tone generator stop and start control. setting this to high will start the tone - generator. after the tone - generator has finished it will reset the register to 0. in continuous mode, setting it to 0 will stop the tone generation. 6:5 r/w (reserved) 00 4 r/w dmtf_en 0 dtmf enable 0 = use values in the freq1 and freq2 registers to generate sine wave(s) 1 = use values from the dmtf_reg to generate sine - waves 3:0 r/w dmtf_reg 0000 the dtmf key pad values 0 to 15.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 114 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xb5 tone_gen _cfg2 7:4 r/w gain 0000 0000 = 0 db 0001 = - 3 db 0010 = - 6 db 0011 = - 9 db continuing in - 3 db steps to 1111 = - 45 db 3:2 r/w (reserved) 00 1:0 r/w swg_sel 00 sine wave select: 00 = sum of both swg values is mixed into the audio 01 = only swg1 value is output 10 = only swg2 value is output 11 = sum of both swg values is mixed into the audio. register address bit type label default description 0xb6 tone_gen _cycles 7:3 r/w (reserved) 00000 2:0 r/w beep_cycles 000 number of beep cycles required. 000 = 1 cycle 001 = 2 cycles 010 = 4 cycles 011 = 8 cycles 100 = 16 cycles 101 = 32 cycles 110 and 111 = infinite (until start_stopn is set to 0) register address bit type label default description 0xb7 tone_gen _freq1_l 7:0 r/w freq1_l 0x55 lower two bytes of the four - byte number used to calculate the output frequency for the first sine wave generator (swg1). the output frequency is dependent on the sample rate for sample rates (sr) = 8/12/16/24/32/48/96 khz: freq1_ u & freq1_l = (2^16 * (f hz /12000)) - 1 for sample rates (sr) = 11.025/22.05/44.4/88.2 khz: freq1_u & freq1_l =(2^16 * (f hz /11025)) - 1
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 115 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xb8 tone_gen _freq1_u 7:0 r/w freq1_u 0x15 upper two bytes of the four - byte number used to calculate the output frequency for the first sine wave generator (swg1). the output frequency is dependent on the sample rate for sample rates (sr) = 8/12/16/24/32/48/96 khz: freq1_u & freq1_l = (2^16 * (f hz /12000)) - 1 for sample rates (sr) = 11.025/22.05/44.4/88.2 khz: freq1_u & freq1_l =(2^16 * (f hz /11025)) - 1 register address bit type label default description 0xb9 tone_gen _freq2_l 7:0 r/w freq2_l 0x00 lower two bytes of the four - byte number used to calculate the output frequency for the second sine wave generator (swg2). the output frequency is dependent on the sample rate for sample rates (sr) = 8/12/16/24/32/48/96 khz: freq2_u & freq2_l = (2^16 * (f hz /12000)) - 1 for sample rates (sr) = 11.025/22.05/44.4/88.2 khz freq2_u & freq2_l =(2^16 * (f hz /11025)) - 1 register address bit type label default description 0xba tone_gen _freq2_u 7:0 r/w freq2_u 0x40 upper two bytes of the four - byte number used to calculate the output frequency for the second sine wave generator (swg2). the output frequency is dependent on the sample rate for sample rates (sr) = 8/12/16/24/32/48/96 khz: freq2_u & freq2_l = (2^16 * (f hz /12000)) - 1 for sample rates (sr) = 11.025/22.05/44.4/88.2 khz freq2_u & freq2_l =(2^16 * (f hz /11025)) - 1
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 116 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xbb tone_gen _on_per 7:6 r/w (reserved) 00 5:0 r/w beep_on_per 000010 beep cycle on - period control 00 0001 = 10 ms 00 0010 = 20 ms 00 0011 = 30 ms continuing in 10 ms steps to... 01 0100 = 200ms then 01 0101 to 01 1000 = reserved then... 01 1001 = 250 ms 01 1010 = 300 ms and continuing in 50 ms steps to... 11 1100 = 2000 ms 11 1 101 = reserved 11 1110 = reserved 11 1111 = continuous
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 117 of 129 ? 2015 dialog semiconductor register address bit type label default description 0xbc tone_gen _off_per 7:6 r/w (reserved) 00 5:0 r/w beep_off_per 000001 beep cycle off - period control 00 0001 = 10 ms 00 0010 = 20 ms 00 0011 = 30 ms continuing in 10 ms steps to... 01 0100 = 200ms then 01 0101 to 01 1000 = reserved then... 01 1001 = 250 ms 01 1010 = 300 ms and continuing in 50 ms steps to... 11 1100 = 2000 ms 11 1101 = reserved 11 1110 = reserved 11 1111 = continuous register address bit type label default description 0xe0 system_s tatus 7:2 r/w (reserved) 000000 1 ro sc2_busy 0 indicates the current status of system controller 2 0 = complete 1 = busy 0 ro sc1_busy 0 indicates the current status of system controller 1 0 = complete 1 = busy register address bit type label default description 0xfd system_a ctive 7:1 r/w (reserved) 0000000 0 r/w system_activ e 0 switch off the oscillator 0 = oscillator off 1 = oscillator on
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 118 of 129 ? 2015 dialog semiconductor 15 package information 15.1 package outlines figure 35 : DA7212 package outline drawing
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 119 of 129 ? 2015 dialog semiconductor 15.2 soldering information refer to the jedec standard j - std - 020 for relevant soldering information. this document can be downloaded from http:// www.jedec.org . 16 ordering information the ordering number consists of the part number followed by a suffix indicating the packing method. for details and availability, please contact dialog semiconductors local sales representative. table 37 : ordering i nformation part number package shipment form pack quantity DA7212 - 01 um2 34 - bump csp pb free/green tape and reel 45 00 DA7212 - 01um6 34 - bump csp pb free/green tray/waffle pack (engineering samples only - not for mass production) 98
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 120 of 129 ? 2015 dialog semiconductor applications information appendix a a.1 codec initialisation depending on the specific application, some general settings need to be set. examples of these settings include the sample rate, the pll, and the digital audio i nterface. then the amplifiers, the mixers and channels of the adc/dac have to be configured and enabled via their respective control registers. an example sequence is shown below: 1. configure clock mode as required for operation, (e.g. pll byp ass / pll etc) 2. configure the digital audio interface 3. configure the charge pump if the headphone path is in use. 4. set input and output mixer paths and gains 5. enable input and o utput paths using the level 2 system c ontroller (slc2) a.2 automatic alc calibration when using the automatic level control (alc) in sync - mode the dc offset between the digital and analogue pgas must be cancelled. this is performed automatically if the following procedure is performed: 1. enable microphone amplifiers unmuted 2. mute microphones 3. enable input mixer and adc unmuted 4. enable aif interface 5. set alc_auto_calib_en in alc_ctrl1 to 1 (alc_ctrl1 = 0x10). this bit will auto - clear when calibration is complete. 6. when calibration is complete, enable the alc with alc_sync_mode and alc_offset_en e nabled (alc_ctrl1 = 0x8b). 7. unmute microphones . the calibration routine requires the full signal path from microphone to adc to be enabled and a clock to be present. the calibration routine using mic1_p and mic2_p and with the device in slave mode is out lined in table 38 .
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 121 of 129 ? 2015 dialog semiconductor table 38 : offset calibration, mic1_p and mic2_p single ended, slave mode instructions registers affected value enable master bias 0x23 0x80 enable aif and setup clocks (for 44.1 khz, i2s, slave mode) 0x29 0xc8 enable the microphones unmuted 0x63 0x64 0x84 0x84 mute the microphones 0x63 0x64 0xc4 0xc4 enable the input mixers unmuted 0x65 0x66 0xa8 0xa8 route the microphone to the mixers 0x32 0x33 0x04 0x04 enable the adc unmuted 0x67 0x68 0xa0 0xa0 calibrate offset 0x2b 0x10 wait until offset bit has been cleared wait until 0x2b = 0x00 enable alc 0x2b 0x8b unmute microphones 0x63 0x64 0xa8 0xa8 other clocking and microphone setups are also possible by changing their respective registers. once this calibration is complete the record path with automatic level control is active. a.3 troubleshooting 0x2b should automatically clear after 256 samples (5.33ms at 48 khz). if 0x2b does not return 0x00 after 256 samples this indicates a setup error. if this occurs check that the microphone is enabled and muted, the mixer is enabled with the microphone input selected and unmuted and that the adc is enabled and unmute d. it is also critical that an mclk and bclk are present on the device. bclk can be provided either from the aif interface in slave mode or generated internally by having the device in master mode.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 122 of 129 ? 2015 dialog semiconductor components appendix b the following recommended components are exam ples selected from requirements of a typical application. the electrical characteristics (that is, the supported voltage/current ranges) have to be cross - checked and component types may need to be adapted from the individual needs of the target circuitry. b.1 audio inputs table 39 : audio inputs pin name bump/pin power domain description type mic1_p c17 vdd_a differential mic. input 1 (positive) / single - ended mic. input 1 (left) analogue input mic1_n b16 vdd_a differential mic. input 1 (negative) / single - ended mic. input 2 (left) analogue input mic2_p d16 vdd_a differential mic. input 2 (positive) / single - ended mic. input 1 (right) analogue input mic2_n c15 vdd_a differential mic. input 2 (negative) / single - ended mic. input 2 (right) analogue input aux_l c13 vdd_a single - ended auxiliary input (left) analogue input aux_r d14 vdd_a single - ended auxiliary input (right) analogue input the DA7212 microphone inputs can be configured to accommodate single - ended or differential microphones and line inputs. these are accompanied by two dedicated single ended auxiliary input pins. the internal input mixer allows all inputs to be mixed prior to the adc. analogue bypass paths exist directly from the aux inputs to the output mixers and from the input mixer to the output mixer should the adc not be required. a dc blocking capacitor is required for each used analogue input bump used in the target application . the choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin which can be found in the input mixing units section of the datasheet. ? = 1 2 ? . ? . ? ? where f c is the 3 db cut off frequ ency of the low pass filter (typically 20 hz for audio applications). a 1 f capacitor is suitable for most applications. due to their high stability tantalum capacitors are particularly suitable for this application. ceramic equivalents with an x5r dielec tric are recommended as a cost effective alternative. care should be taken to ensure that the desired capacitance is maintained over operating temperature and voltage. z5u dielectric ceramics should be avoided due to their susceptibility to microphonic eff ects. unused input bumps can be left floating or connected via a capacitor to ground.
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 123 of 129 ? 2015 dialog semiconductor b.2 microphone b ias table 40 : microphone bias pin name bump/pin power domain description type micbias1 a15 vdd_mic microphone bias output 1 analogue output micbias2 a17 vdd_mic microphone bias output 2 analogue output a 1 f capacitor to gnd_a should be used to decouple the micbias output. figure 36 : m icbias decoupling b.3 digital m icrophone table 41 : digital microphones pin name bump/pin power domain description type dmicclk c17 vdd_mic digital microphone clock digital output dmicin b16 vdd_mic digital microphone data digital input these pins can be routed directly to a digital microphone. in stereo mode they can be connected to two digital microphones with one configured to send data on the rising clock edge and the other on the falling edge. the clock output operates at 1.5 mhz or 3 mhz. the appropriate layout considera tions for clock signals should be followed. b.4 audio o utputs table 42 : headphone outputs pin name bump/pin power domain description type hp_l a3 vdd_a true - ground headphone output (left) analogue output hp_r a5 vdd_a true - ground headphone output (right) analogue output gnd_sense b4 vdd_a ground reference for headphone output analogue input DA7212 contains a capless true - ground class - g headphone amplifier with a ground sense connection. for optimum noise immunity the headphone ground sense should be tracked between the hp_l and hp_r signals before being grounded at the headphone connector. in this configuration the ground sense connector cancels common mode noise on the headphone from the pcb. figure 37 : recommended h eadphone layout m i c b i a s 1 m 1 1 m i c b i a s 1 f m i c b i a s 2 a 1 7 m i c b i a s 2 1 f a 1 5 m i c b i a s 1 m 1 1 m i c b i a s a 3 h p _ l a 5 h p _ r g n d _ s e n s e b 4
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 124 of 129 ? 2015 dialog semiconductor table 43 : speaker outputs pin name bump/pin power domain description type sp_p b12 vdd_sp differential speaker output (pos) analogue output sp_n a13 vdd_sp differential speaker output (neg) analogue output the DA7212 has a differential class - ab speaker driver that can output 1.2 w into an 8 ohm speaker. these pins can be connected directly to an external speaker or receiver or as a differential line output. for common mode noise immunity sp_p and sp_n should be treated as a differential pair where possible. a dc blocking capacitor is required when the speaker is being used to drive a line level output. the choice of capacitor is determined by the filter that is formed b etween that capacitor and the impedance of the load. ? = 1 2 ? . ? . ? ? where f c is the 3 db cut off frequency of the low pass filter (typically 20 hz for audio applications). a 1 f capacitor is suitable for most applications. due to their high stability tantalum capacitors are particularly suitable for this application. ceramic equivalents with an x5r dielectric are recommended as a cost effective alternative. care should be taken to ensure that the desired capacitance is maintained over operating tempera ture and voltage. if the speaker/line output is unused the output pins can be left floating or conne cted via a capacitor to ground. b.5 headphone c harge pump table 44 : headphone charge pump pin name bump/pin power domain description typ e hpcsp a1 vdd_a chargepump reservoir capacitor (pos) charge pump hpcsn c1 vdd_a chargepump reservoir capacitor (neg) charge pump hpcfp d2 vdd_a chargepump flying capacitor (pos) charge pump hpcfn c3 vdd_a chargepump flying capacitor (neg) charge pump a 1 f reservoir capacitor is required between the hpcsp and gnd_cp and between hpcsn and gnd_cp. for best performance the capacitors should be fitted as near to the device as possible. figure 38 : charge pump d ecoupling a 1 f flying capacitor is required between hpcfp and hpcfn. for best performance the capacitor should be fitted as near to the device as possible. figure 39 : charge pump flying c apacitor m 1 1 m i c b i a s 1 f c 1 h p c s n 1 f a 1 h p c s p m 1 1 m i c b i a s 1 f c 3 h p c f n d 2 h p c f p
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 125 of 129 ? 2015 dialog semiconductor to ensure stable charge pump operation the effective series resistance of the flying capacitor should be kept to a minimum. this can be achieved by selecting an appropriate capacitor dielectric (x5r, x7r) and ensuring that the capacitor is place d as near to the device as possible. ideally the connection between the pins and the capacitor should not run through vias (connected on top layer of pcb only ). b.6 digital i nterfaces table 45 : digital interfaces - i2c pin name bump/pin power domain description type sda c9 vdd_io i2c bi - directional data digital input / output scl d8 vdd_io i2c clock input digital input the i2c data and clock lines are powered from vdd_io. both i2c line require a pull up to vdd_io. the value of this pull up is dependent on i2c bus speed, bus length and supply voltage. a 2.2 k? resistor is satisfactory in most applications. figure 40 : i2c pull ups table 46 : digital interfaces - i2s pin name bump/p in power d omain description type datin c5 vdd_io dai data input digital output datout c7 vdd_io dai data output digital input bclk d4 vdd_io dai bit clock digital input / output wclk d6 vdd_io dai word clock (l/r select) digital input / output mclk c11 vdd_io master clock digital input the dai interface pins should be treated as clock signals and the appropriate layout rules for routing clocks should be adhered to. s c l s d a c 9 d 8 v d d _ i o 2 k 2 ? 2 k 2 ?
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 126 of 129 ? 2015 dialog semiconductor b.7 references table 47 : references pin name bump/p in power d omain description type dacref a7 vdd_a audio dac reference capacitor reference vmid a9 vdd_a audio mid - rail reference capacitor reference vref b8 vdd_a bandgap reference capacitor reference a 1 f capacitor should be connected between each of the references and gnd_a. for best performance the capacitors should be fitted as near to the device as possible. figure 41 : reference c ap acitors b.8 supplies table 48 : power supplies pin name bump/p in power d omain description type vdd_a b6 min: 1.7 v max: 2.5 v supply for analogue circuits / supply for headphone charge pump power supply vdd_io d10 min: 1.6 v max: 3.6 v supply for digital interfaces power supply vdd_sp a11 min: 0.95 v max: 5.25 v supply for speaker driver power supply vdd_mic b14 min: 1.8 v max: 3.6 v supply for microphone bias circuits power supply vdig d12 output of internal regulator. power supply decoupling capacitors are recommended between all supplies and gnd_a. these capacitors should be located as near to the device as possible. figure 42 : power supply d ecoupling m 1 1 m i c b i a s 1 f b 8 v r e f 1 f a 9 v m i d a 7 1 f d a c r e f m 1 1 m i c b i a s 1 f d 1 2 v d i g 1 f b 1 4 v d d _ m i c a 1 1 1 f v d d _ s p d 1 0 1 f v d d _ i o b 6 1 f v d d _ a 1 . 7 v - 2 . 5 v 0 . 9 5 v - 5 . 2 5 v 1 . 8 v - 3 . 6 v 1 . 6 v - 3 . 6 v
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 127 of 129 ? 2015 dialog semiconductor b.9 ground table 49 : ground pin name bump/p in power d omain description type gnd_a b10 analogue ground power ground gnd_cp b2 digital/chargepump ground power ground gnd_a and gnd_cp should be connected directly to the system ground . b.10 capacitor s election ceramic capacitors are manufactured with a variety of dielectrics, each with a different behaviour over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature ra nge, dc bias conditions and low equivalent series resistance (esr). x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use because of their poor temperature an d dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: ? ??? = ? ??? ? ( 1 ? ?????? ) ? ( 1 ? ??? ) where: ceff is the ef fective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. these figures can be found in the manufacturers datasheet. in the example below, the worst - case temperatu re coefficient (tempco) over ?55c to +85c is assumed to be 15 %. the tolerance of the capacitor (tol) is assumed to be 1 0 %, and cout is 0.65 f at 1.8 v. substituting these values in the equation yields ? ??? = 0 . 65 ?? ? ( 1 ? 0 . 15 ) ? ( 1 ? 0 . 1 ) = 0 . 497 ?? table 50 : recommended capacitor types application value size temp. c har. tolerance rated v oltage type vdd_io, vref, vdd_mic, vdd_sp, vdd_a, vdig, dacref, vmid, hpcfp/hpcfn, hpcsp, hpcsn, micbias1, micbias2, aux_l, aux_r 14 x 1 f 0201 x5r +/ - 15 % +/ - 10 % 6.3 v murata grm033r60j105m
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 128 of 129 ? 2015 dialog semiconductor pcb l ayout guidelines appendix c DA7212 uses dialog semiconductors route easy? technology allowing the device to be routed using conventional, low cost, pcb technology. all device balls are routable on the top level and conventional plated through hole vias can be used throughout. this desig n is fully realisable using a 2 - layer pcb however for optimum performance it is recommended that a 4 - layer pcb is used with layers 2 and 3 as solid ground planes. decoupling and reference capacitors should be located as close to the device as possible and appropriately sized tracks should be used for all power connections. figure 43 : example l ayout c.1 layout and s chematic support copies of the evaluation board schematics and layout are available on request to aid in pcb development. dialog semiconductor also offer a schematic and layout review service for all designs utilising dialogs devices. please contact your local dialog semiconductor office if you wish to utilise this service. c.2 general r ecommendations appropriate trace width an d number of vias should be used for all power supply paths a common ground plane should be used, which allows proper electrical and thermal performance noise - sensitive analogue signals such as feedback lines or clock connections should be kept away from tr aces carrying pulsed analogue or digital signals. this can be achieved by separation (distance) or by shielding with quiet signals or ground traces decoupling capacitors should be x5r ceramics and should be placed as near to the device as possible charge p ump capacitors should be x5r ceramics and should be placed as near to the device as possible
DA7212 ultra - low power stereo codec company confidential datasheet revision 3c 24 - nov - 2015 129 of 129 ? 2015 dialog semiconductor status d efinitions revi sion datas heet s tatus product s tatus definition 1. target development this data sheet contains the design specifications for product development. specifications may be changed in any manner without notice. 2. preliminary qualification this data sheet contains the specifications and preliminary characteri s ation data for products in pre - production. s pe cifications may be changed at any time without notice in order to improve the design. 3. final production this data sheet contains the final specifications for products in volume production. the specifications may be changed at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via customer product notifications. 4. obsolete archived this data sheet contains the specifications for discontinued products. the information is provided for referenc e only. disclaimer information in this document is believed to be accurate and reliable. however, dialog semiconductor does not give any represent ations or warranties, expressed or implied, as to the accuracy or completeness of such information. dialog s emiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any information source outside of dialog semiconductor. dialog semiconductor reserves the right to change without notice the information published i n this document, including without limitation the specification and the design of the related semiconductor products, software and applications. applications, software, and semiconductor products described in this document are for illustrative purposes on ly. dialog semiconductor makes no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. unless otherwise agreed in writing, such testing or mod ification is the sole responsibility of the customer and dialog semiconductor excludes all liability in this respect. customer notes that nothing in this document may be construed as a license for customer to use the dialog semiconductor products, softwar e and applications referred to in this document. such license must be separately sought by customer with dialog semiconductor. all use of dialog semiconductor products, software and applications referred to in this document are subject to dialog semiconduc tors standard terms and conditions of sale , unless otherwise stated. ? dialog semiconductor. all rights reserved. rohs c ompliance dialog semiconductor complies to european d irective 2001/95/ec and from 2 january 2013 onwards to european directive 2011/65/eu concerning restriction of hazardous substances (rohs/rohs2). dialog semiconductors statement on rohs can be found on the customer portal https://support.diasemi.com/ . rohs certificates from our sup pliers are available on request. contacting dialog semiconductor united kingdom (headquarters) dialog semiconductor (uk) ltd phone: +44 1793 757700 germany dialog semiconductor gmbh phone: +49 7021 805 - 0 the netherlands dialog semiconductor b.v. phone: +31 73 640 8822 north america dialog semiconductor inc. phone: +1 408 845 8500 japan dialog semiconductor k. k. phone: +81 3 5425 4567 taiwan dialog semiconductor taiwan phone: +886 281 786 222 singapore dialog semiconductor singapore phone: +65 64 8499 29 hong kong dialog semiconductor hong kong phone: +852 3769 5200 korea dialog semiconductor korea phone: +82 2 3469 8200 china (shenzhen) dialog semiconductor china phone: +86 755 2981 3 669 china (shanghai) dialog semiconductor china phone: +86 21 5424 9058 email: enquiry@diasemi.com web site: www.dialog - semiconductor.com

▲Up To Search▲

Price & Availability of DA7212

	To Download DA7212 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .